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authorAlex Crichton <alex@alexcrichton.com>2018-12-14 09:05:31 -0800
committerAlex Crichton <alex@alexcrichton.com>2018-12-14 09:05:31 -0800
commitc811915eafb349759d2bba9d7a39a53aef02bb3d (patch)
treeb072af96663be962f5e5c5745ff92b61f35c4232 /src
parent7d03617bab24a689bc704e71e509b9c11c655f26 (diff)
downloadrust-c811915eafb349759d2bba9d7a39a53aef02bb3d.tar.gz
rust-c811915eafb349759d2bba9d7a39a53aef02bb3d.zip
std: Activate compiler_builtins `mem` feature for no_std targets
This was an accidental regression from #56092, but for `no_std` targets
being built and distributed we want to be sure to activate the
compiler-builtins `mem` feature which demangles important memory-related
intrinsics.
Diffstat (limited to 'src')
-rw-r--r--src/bootstrap/compile.rs4
-rw-r--r--src/liballoc/Cargo.toml3
2 files changed, 6 insertions, 1 deletions
diff --git a/src/bootstrap/compile.rs b/src/bootstrap/compile.rs
index c84abe42a63..689d0530f8b 100644
--- a/src/bootstrap/compile.rs
+++ b/src/bootstrap/compile.rs
@@ -155,7 +155,9 @@ pub fn std_cargo(builder: &Builder,
         cargo
             .args(&["-p", "alloc"])
             .arg("--manifest-path")
-            .arg(builder.src.join("src/liballoc/Cargo.toml"));
+            .arg(builder.src.join("src/liballoc/Cargo.toml"))
+            .arg("--features")
+            .arg("compiler-builtins-mem");
     } else {
         let features = builder.std_features();
 
diff --git a/src/liballoc/Cargo.toml b/src/liballoc/Cargo.toml
index b7faee1bc7d..b2eb3566c04 100644
--- a/src/liballoc/Cargo.toml
+++ b/src/liballoc/Cargo.toml
@@ -28,3 +28,6 @@ path = "../liballoc/benches/lib.rs"
 name = "vec_deque_append_bench"
 path = "../liballoc/benches/vec_deque_append.rs"
 harness = false
+
+[features]
+compiler-builtins-mem = ['compiler_builtins/mem']