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authorErik Desjardins <erikdesjardins@users.noreply.github.com>2024-02-25 00:43:03 -0500
committerErik Desjardins <erikdesjardins@users.noreply.github.com>2024-03-05 18:54:45 -0500
commit96a72676d1134f58c378b0b8003922b09b9f1e5f (patch)
treef78c6972555bd2bd116ec9d1941b7798da8c3d90 /tests/codegen/align-struct.rs
parent3c029725f5a198f4ccb1332bece98c2b50dbce01 (diff)
downloadrust-96a72676d1134f58c378b0b8003922b09b9f1e5f.tar.gz
rust-96a72676d1134f58c378b0b8003922b09b9f1e5f.zip
use [N x i8] for byval/sret types
This avoids depending on LLVM's struct types to determine the size of
the byval/sret slot.
Diffstat (limited to 'tests/codegen/align-struct.rs')
-rw-r--r--tests/codegen/align-struct.rs4
1 files changed, 0 insertions, 4 deletions
diff --git a/tests/codegen/align-struct.rs b/tests/codegen/align-struct.rs
index 31859152830..dbbb85bee6f 100644
--- a/tests/codegen/align-struct.rs
+++ b/tests/codegen/align-struct.rs
@@ -5,7 +5,6 @@
 
 #[repr(align(64))]
 pub struct Align64(i32);
-// CHECK: %Align64 = type { i32, [15 x i32] }
 
 pub struct Nested64 {
     a: Align64,
@@ -13,19 +12,16 @@ pub struct Nested64 {
     c: i32,
     d: i8,
 }
-// CHECK: %Nested64 = type { %Align64, i32, i32, i8, [55 x i8] }
 
 pub enum Enum4 {
     A(i32),
     B(i32),
 }
-// No Aggregate type, and hence nothing in LLVM IR.
 
 pub enum Enum64 {
     A(Align64),
     B(i32),
 }
-// CHECK: %Enum64 = type { i32, [31 x i32] }
 
 // CHECK-LABEL: @align64
 #[no_mangle]