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authorScott McMurray <scottmcm@users.noreply.github.com>2025-03-07 02:40:40 -0800
committerScott McMurray <scottmcm@users.noreply.github.com>2025-03-12 22:39:43 -0700
commit91af4aa2e2b33635893a75d900f305f993df1739 (patch)
tree7c7caa4f1835315dab81226510cead6459303e45 /tests/codegen/range-loop.rs
parent8536f201ffdb2c24925d7f9e87996d7dca93428b (diff)
downloadrust-91af4aa2e2b33635893a75d900f305f993df1739.tar.gz
rust-91af4aa2e2b33635893a75d900f305f993df1739.zip
Allow more top-down inlining for single-BB callees
This means that things like `<usize as Step>::forward_unchecked` and `<PartialOrd for f32>::le` will inline even if we've already done a bunch of inlining to find the calls to them.
Diffstat (limited to 'tests/codegen/range-loop.rs')
-rw-r--r--tests/codegen/range-loop.rs44
1 files changed, 44 insertions, 0 deletions
diff --git a/tests/codegen/range-loop.rs b/tests/codegen/range-loop.rs
new file mode 100644
index 00000000000..b131beb40dd
--- /dev/null
+++ b/tests/codegen/range-loop.rs
@@ -0,0 +1,44 @@
+//@ ignore-std-debug-assertions
+//@ compile-flags: -Copt-level=3 -C no-prepopulate-passes
+
+#![crate_type = "lib"]
+
+// Ensure that MIR optimizations have cleaned things up enough that the IR we
+// emit is good even without running the LLVM optimizations.
+
+// CHECK-NOT: define
+
+// CHECK-LABEL: define{{.+}}void @call_for_zero_to_n
+#[no_mangle]
+pub fn call_for_zero_to_n(n: u32, f: fn(u32)) {
+    // CHECK: start:
+    // CHECK-NOT: alloca
+    // CHECK: %[[IND:.+]] = alloca [4 x i8]
+    // CHECK-NEXT: %[[ALWAYS_SOME_OPTION:.+]] = alloca
+    // CHECK-NOT: alloca
+    // CHECK: store i32 0, ptr %[[IND]],
+    // CHECK: br label %[[HEAD:.+]]
+
+    // CHECK: [[HEAD]]:
+    // CHECK: %[[T1:.+]] = load i32, ptr %[[IND]],
+    // CHECK: %[[NOT_DONE:.+]] = icmp ult i32 %[[T1]], %n
+    // CHECK: br i1 %[[NOT_DONE]], label %[[BODY:.+]], label %[[BREAK:.+]]
+
+    // CHECK: [[BREAK]]:
+    // CHECK: ret void
+
+    // CHECK: [[BODY]]:
+    // CHECK: %[[T2:.+]] = load i32, ptr %[[IND]],
+    // CHECK: %[[T3:.+]] = add nuw i32 %[[T2]], 1
+    // CHECK: store i32 %[[T3]], ptr %[[IND]],
+
+    // CHECK: store i32 %[[T2]]
+    // CHECK: %[[T4:.+]] = load i32
+    // CHECK: call void %f(i32{{.+}}%[[T4]])
+
+    for i in 0..n {
+        f(i);
+    }
+}
+
+// CHECK-NOT: define