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authorJubilee Young <workingjubilee@gmail.com>2023-07-11 19:17:56 -0700
committerJubilee Young <workingjubilee@gmail.com>2023-07-11 20:21:32 -0700
commit7dc049c378743a9e60dccf47143df9c0052bfe2b (patch)
tree33151e958c4caf92d311fad17d8604217a63035f /tests/codegen
parent81dc91efbd3272cb055df9662833c1af8aeb1dd2 (diff)
downloadrust-7dc049c378743a9e60dccf47143df9c0052bfe2b.tar.gz
rust-7dc049c378743a9e60dccf47143df9c0052bfe2b.zip
Reenable all cases of simd-wide-sum
Diffstat (limited to 'tests/codegen')
-rw-r--r--tests/codegen/simd-wide-sum.rs7
1 files changed, 3 insertions, 4 deletions
diff --git a/tests/codegen/simd-wide-sum.rs b/tests/codegen/simd-wide-sum.rs
index 87ef29b351f..3116f9597bc 100644
--- a/tests/codegen/simd-wide-sum.rs
+++ b/tests/codegen/simd-wide-sum.rs
@@ -52,9 +52,8 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
 #[no_mangle]
 // CHECK-LABEL: @wider_reduce_into_iter
 pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
-    // FIXME MIR inlining messes up LLVM optimizations.
-    // WOULD-CHECK: zext <8 x i8>
-    // WOULD-CHECK-SAME: to <8 x i16>
-    // WOULD-CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
+    // CHECK: zext <8 x i8>
+    // CHECK-SAME: to <8 x i16>
+    // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16>
     x.to_array().into_iter().map(u16::from).sum()
 }