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authorbors <bors@rust-lang.org>2023-08-23 19:48:39 +0000
committerbors <bors@rust-lang.org>2023-08-23 19:48:39 +0000
commit5680fa18feaa87f3ff04063800aec256c3d4b4be (patch)
treef0daae2bd1d2aea53a44c261bd4f3e359a436567 /tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir
parentf155f8c3d9b6f63f1752dc205665869c475d3c1f (diff)
parent298ec5258f8e5f1211734bcb43c89aa184d3ca1b (diff)
downloadrust-1.72.0.tar.gz
rust-1.72.0.zip
Auto merge of #115140 - wesleywiser:turn_off_mir_sroa, r=cuviper 1.72.0
Disable MIR SROA optimization by default

Turn off the MIR SROA optimization by default to prevent incorrect debuginfo generation and rustc ICEs caused by invalid LLVM IR being created.

Related to #115113

r? `@cuviper`
cc `@saethlin`
Diffstat (limited to 'tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir')
-rw-r--r--tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir34
1 files changed, 23 insertions, 11 deletions
diff --git a/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir b/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir
index 800308c2e0b..70461b44559 100644
--- a/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir
+++ b/tests/mir-opt/pre-codegen/checked_ops.checked_shl.PreCodegen.after.mir
@@ -7,10 +7,13 @@ fn checked_shl(_1: u32, _2: u32) -> Option<u32> {
     scope 1 (inlined core::num::<impl u32>::checked_shl) {
         debug self => _1;
         debug rhs => _2;
-        let mut _7: bool;
+        let mut _7: (u32, bool);
+        let _8: u32;
+        let _9: bool;
+        let mut _10: bool;
         scope 2 {
-            debug a => _5;
-            debug b => _6;
+            debug a => _8;
+            debug b => _9;
         }
         scope 3 (inlined core::num::<impl u32>::overflowing_shl) {
             debug self => _1;
@@ -35,8 +38,10 @@ fn checked_shl(_1: u32, _2: u32) -> Option<u32> {
     }
 
     bb0: {
+        StorageLive(_8);
+        StorageLive(_9);
+        StorageLive(_7);
         StorageLive(_5);
-        StorageLive(_6);
         StorageLive(_4);
         StorageLive(_3);
         _3 = const 31_u32;
@@ -44,17 +49,24 @@ fn checked_shl(_1: u32, _2: u32) -> Option<u32> {
         StorageDead(_3);
         _5 = ShlUnchecked(_1, _4);
         StorageDead(_4);
+        StorageLive(_6);
         _6 = Ge(_2, const _);
-        StorageLive(_7);
-        _7 = unlikely(_6) -> [return: bb1, unwind unreachable];
+        _7 = (move _5, move _6);
+        StorageDead(_6);
+        StorageDead(_5);
+        _8 = (_7.0: u32);
+        _9 = (_7.1: bool);
+        StorageDead(_7);
+        StorageLive(_10);
+        _10 = unlikely(_9) -> [return: bb1, unwind unreachable];
     }
 
     bb1: {
-        switchInt(move _7) -> [0: bb2, otherwise: bb3];
+        switchInt(move _10) -> [0: bb2, otherwise: bb3];
     }
 
     bb2: {
-        _0 = Option::<u32>::Some(_5);
+        _0 = Option::<u32>::Some(_8);
         goto -> bb4;
     }
 
@@ -64,9 +76,9 @@ fn checked_shl(_1: u32, _2: u32) -> Option<u32> {
     }
 
     bb4: {
-        StorageDead(_7);
-        StorageDead(_6);
-        StorageDead(_5);
+        StorageDead(_10);
+        StorageDead(_9);
+        StorageDead(_8);
         return;
     }
 }