Auto merge of #112418 - ferrocene:pa-mir-opt-panic, r=ozkanonur,saethlin

Add support for targets without unwinding in `mir-opt`, and improve `--bless` for it

The main goal of this PR is to add support for targets without unwinding support in the `mir-opt` test suite, by adding the `EMIT_MIR_FOR_EACH_PANIC_STRATEGY` comment. Similarly to 32bit vs 64bit, when that comment is present, blessed output files will have the `.panic-unwind` or `.panic-abort` suffix, and the right one will be chosen depending on the target's panic strategy.

The `EMIT_MIR_FOR_EACH_PANIC_STRATEGY` comment replaced all the `ignore-wasm32` comments in the `mir-opt` test suite, as those comments were added due to `wasm32` being a target without unwinding support. The comment was also added on other tests that were only executed on x86 but were still panic strategy dependent.

The `mir-opt` suite was then blessed, which caused a ton of churn as most of the existing output files had to be renamed and (mostly) duplicated with the abort strategy.

---

After [asking on Zulip](https://rust-lang.zulipchat.com/#narrow/stream/131828-t-compiler/topic/mir-opt.20tests.20and.20panic.3Dabort), the main concern about this change is it'd make blessing the `mir-opt` suite even harder, as you'd need to both bless it with an unwinding target and an aborting target. This exacerbated the current situation, where you'd need to bless it with a 32bit and a 64bit target already.

Because of that, this PR also makes significant enhancements to `--bless` for the `mir-opt` suite, where it will automatically bless the suite four times with different targets, while requiring minimal cross-compilation.

To handle the 32bit vs 64bit blessing, there is now an hardcoded list of target mapping between 32bit and 64bit. The goal of the list is to find a related target that will *probably* work without requiring additional cross-compilation toolchains on the system. If a mapping is found, bootstrap will bless the suite with both targets, otherwise just with the current target.

To handle the panic strategy blessing (abort vs unwind), I had to resort to what I call "synthetic targets". For each of the target we're blessing (so either the current one, or a 32bit and a 64bit depending on the previous paragraph), bootstrap will extract the JSON spec of the target and change it to include `"panic-strategy": "abort"`. It will then build the standard library with this synthetic target, and bless the `mir-opt` suite with it.

As a result of these changes, blessing the `mir-opt` suite will actually bless it two or four times with different targets, ensuring all possible variants are actually blessed.

---

This PR is best reviewed commit-by-commit.

r? `@jyn514`
cc `@saethlin` `@oli-obk`

1 files changed, 145 insertions, 0 deletions

diff --git a/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir
new file mode 100644
index 00000000000..28ec230619f
--- /dev/null
+++ b/tests/mir-opt/pre-codegen/range_iter.forward_loop.PreCodegen.after.panic-unwind.mir
@@ -0,0 +1,145 @@
+// MIR for `forward_loop` after PreCodegen
+
+fn forward_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () {
+    debug start => _1;                   // in scope 0 at $DIR/range_iter.rs:+0:21: +0:26
+    debug end => _2;                     // in scope 0 at $DIR/range_iter.rs:+0:33: +0:36
+    debug f => _3;                       // in scope 0 at $DIR/range_iter.rs:+0:43: +0:44
+    let mut _0: ();                      // return place in scope 0 at $DIR/range_iter.rs:+0:60: +0:60
+    let mut _4: std::ops::Range<u32>;    // in scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+    let mut _5: std::ops::Range<u32>;    // in scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+    let mut _6: &mut std::ops::Range<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+    let mut _12: std::option::Option<u32>; // in scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+    let mut _15: isize;                  // in scope 0 at $DIR/range_iter.rs:+1:5: +3:6
+    let mut _17: &impl Fn(u32);          // in scope 0 at $DIR/range_iter.rs:+2:9: +2:10
+    let mut _18: (u32,);                 // in scope 0 at $DIR/range_iter.rs:+2:9: +2:13
+    let _19: ();                         // in scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+    scope 1 {
+        debug iter => _5;                // in scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+        let _16: u32;                    // in scope 1 at $DIR/range_iter.rs:+1:9: +1:10
+        scope 2 {
+            debug x => _16;              // in scope 2 at $DIR/range_iter.rs:+1:9: +1:10
+        }
+        scope 4 (inlined iter::range::<impl Iterator for std::ops::Range<u32>>::next) { // at $DIR/range_iter.rs:22:14: 22:24
+            debug self => _6;            // in scope 4 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+            scope 5 (inlined <std::ops::Range<u32> as iter::range::RangeIteratorImpl>::spec_next) { // at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                debug self => _6;        // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                let mut _7: &u32;        // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                let mut _8: &u32;        // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                let mut _11: bool;       // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                let _13: u32;            // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                let mut _14: u32;        // in scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                scope 6 {
+                    debug old => _13;    // in scope 6 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                    scope 7 {
+                    }
+                }
+                scope 8 (inlined cmp::impls::<impl PartialOrd for u32>::lt) { // at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                    debug self => _7;    // in scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+                    debug other => _8;   // in scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+                    let mut _9: u32;     // in scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+                    let mut _10: u32;    // in scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+                }
+            }
+        }
+    }
+    scope 3 (inlined <std::ops::Range<u32> as IntoIterator>::into_iter) { // at $DIR/range_iter.rs:22:14: 22:24
+        debug self => _4;                // in scope 3 at $SRC_DIR/core/src/iter/traits/collect.rs:LL:COL
+    }
+
+    bb0: {
+        _4 = std::ops::Range::<u32> { start: _1, end: _2 }; // scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+        StorageLive(_5);                 // scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+        _5 = move _4;                    // scope 0 at $DIR/range_iter.rs:+1:14: +1:24
+        goto -> bb1;                     // scope 1 at $DIR/range_iter.rs:+1:5: +3:6
+    }
+
+    bb1: {
+        StorageLive(_12);                // scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+        _6 = &mut _5;                    // scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+        StorageLive(_13);                // scope 4 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageLive(_11);                // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageLive(_7);                 // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        _7 = &((*_6).0: u32);            // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageLive(_8);                 // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        _8 = &((*_6).1: u32);            // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageLive(_9);                 // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        _9 = (*_7);                      // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        StorageLive(_10);                // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        _10 = (*_8);                     // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        _11 = Lt(move _9, move _10);     // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        StorageDead(_10);                // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        StorageDead(_9);                 // scope 8 at $SRC_DIR/core/src/cmp.rs:LL:COL
+        StorageDead(_8);                 // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageDead(_7);                 // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        switchInt(move _11) -> [0: bb2, otherwise: bb3]; // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+    }
+
+    bb2: {
+        _12 = Option::<u32>::None;       // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        goto -> bb5;                     // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+    }
+
+    bb3: {
+        _13 = ((*_6).0: u32);            // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageLive(_14);                // scope 6 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        _14 = <u32 as Step>::forward_unchecked(_13, const 1_usize) -> [return: bb4, unwind: bb11]; // scope 7 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+                                         // mir::Constant
+                                         // + span: $SRC_DIR/core/src/iter/range.rs:LL:COL
+                                         // + literal: Const { ty: unsafe fn(u32, usize) -> u32 {<u32 as Step>::forward_unchecked}, val: Value(<ZST>) }
+    }
+
+    bb4: {
+        ((*_6).0: u32) = move _14;       // scope 6 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageDead(_14);                // scope 6 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        _12 = Option::<u32>::Some(_13);  // scope 6 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        goto -> bb5;                     // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+    }
+
+    bb5: {
+        StorageDead(_11);                // scope 5 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        StorageDead(_13);                // scope 4 at $SRC_DIR/core/src/iter/range.rs:LL:COL
+        _15 = discriminant(_12);         // scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+        switchInt(move _15) -> [0: bb6, 1: bb8, otherwise: bb10]; // scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+    }
+
+    bb6: {
+        StorageDead(_12);                // scope 1 at $DIR/range_iter.rs:+3:5: +3:6
+        StorageDead(_5);                 // scope 0 at $DIR/range_iter.rs:+3:5: +3:6
+        drop(_3) -> bb7;                 // scope 0 at $DIR/range_iter.rs:+4:1: +4:2
+    }
+
+    bb7: {
+        return;                          // scope 0 at $DIR/range_iter.rs:+4:2: +4:2
+    }
+
+    bb8: {
+        _16 = ((_12 as Some).0: u32);    // scope 1 at $DIR/range_iter.rs:+1:9: +1:10
+        StorageLive(_17);                // scope 2 at $DIR/range_iter.rs:+2:9: +2:10
+        _17 = &_3;                       // scope 2 at $DIR/range_iter.rs:+2:9: +2:10
+        StorageLive(_18);                // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
+        _18 = (_16,);                    // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
+        _19 = <impl Fn(u32) as Fn<(u32,)>>::call(move _17, move _18) -> [return: bb9, unwind: bb11]; // scope 2 at $DIR/range_iter.rs:+2:9: +2:13
+                                         // mir::Constant
+                                         // + span: $DIR/range_iter.rs:23:9: 23:10
+                                         // + literal: Const { ty: for<'a> extern "rust-call" fn(&'a impl Fn(u32), (u32,)) -> <impl Fn(u32) as FnOnce<(u32,)>>::Output {<impl Fn(u32) as Fn<(u32,)>>::call}, val: Value(<ZST>) }
+    }
+
+    bb9: {
+        StorageDead(_18);                // scope 2 at $DIR/range_iter.rs:+2:12: +2:13
+        StorageDead(_17);                // scope 2 at $DIR/range_iter.rs:+2:12: +2:13
+        StorageDead(_12);                // scope 1 at $DIR/range_iter.rs:+3:5: +3:6
+        goto -> bb1;                     // scope 1 at $DIR/range_iter.rs:+1:5: +3:6
+    }
+
+    bb10: {
+        unreachable;                     // scope 1 at $DIR/range_iter.rs:+1:14: +1:24
+    }
+
+    bb11 (cleanup): {
+        drop(_3) -> [return: bb12, unwind terminate]; // scope 0 at $DIR/range_iter.rs:+4:1: +4:2
+    }
+
+    bb12 (cleanup): {
+        resume;                          // scope 0 at $DIR/range_iter.rs:+0:1: +4:2
+    }
+}