diff options
| -rw-r--r-- | patches/0001-portable-simd-Disable-unsupported-tests.patch | 64 | ||||
| -rw-r--r-- | src/intrinsics/simd.rs | 29 |
2 files changed, 28 insertions, 65 deletions
diff --git a/patches/0001-portable-simd-Disable-unsupported-tests.patch b/patches/0001-portable-simd-Disable-unsupported-tests.patch index e23dea97694..89e2b61c1fc 100644 --- a/patches/0001-portable-simd-Disable-unsupported-tests.patch +++ b/patches/0001-portable-simd-Disable-unsupported-tests.patch @@ -11,44 +11,6 @@ Subject: [PATCH] Disable unsupported tests crates/core_simd/tests/masks.rs | 3 --- 5 files changed, 20 insertions(+), 3 deletions(-) -diff --git a/crates/core_simd/src/masks/full_masks.rs b/crates/core_simd/src/masks/full_masks.rs -index adf0fcb..e7e657e 100644 ---- a/crates/core_simd/src/masks/full_masks.rs -+++ b/crates/core_simd/src/masks/full_masks.rs -@@ -180,6 +180,7 @@ where - super::Mask<T, LANES>: ToBitMaskArray, - [(); <super::Mask<T, LANES> as ToBitMaskArray>::BYTES]: Sized, - { -+ /* - assert_eq!(<super::Mask<T, LANES> as ToBitMaskArray>::BYTES, N); - - // Safety: N is the correct bitmask size -@@ -202,6 +203,8 @@ where - Self::splat(false).to_int(), - )) - } -+ */ -+ panic!(); - } - - #[inline] -@@ -225,6 +228,7 @@ where - where - super::Mask<T, LANES>: ToBitMask<BitMask = U>, - { -+ /* - // LLVM assumes bit order should match endianness - let bitmask = if cfg!(target_endian = "big") { - bitmask.reverse_bits(LANES) -@@ -240,6 +244,8 @@ where - Self::splat(false).to_int(), - )) - } -+ */ -+ panic!(); - } - - #[inline] diff --git a/crates/core_simd/src/vector.rs b/crates/core_simd/src/vector.rs index e8e8f68..7173c24 100644 --- a/crates/core_simd/src/vector.rs @@ -69,31 +31,5 @@ index e8e8f68..7173c24 100644 } impl<T, const LANES: usize> Copy for Simd<T, LANES> -diff --git a/crates/core_simd/tests/masks.rs b/crates/core_simd/tests/masks.rs -index 673d0db..3ebfcd1 100644 ---- a/crates/core_simd/tests/masks.rs -+++ b/crates/core_simd/tests/masks.rs -@@ -78,7 +78,6 @@ macro_rules! test_mask_api { - let mask = core_simd::Mask::<$type, 16>::from_array(values); - let bitmask = mask.to_bitmask(); - assert_eq!(bitmask, 0b1000001101001001); -- assert_eq!(core_simd::Mask::<$type, 16>::from_bitmask(bitmask), mask); - } - - #[test] -@@ -91,13 +90,11 @@ macro_rules! test_mask_api { - let mask = core_simd::Mask::<$type, 4>::from_array(values); - let bitmask = mask.to_bitmask(); - assert_eq!(bitmask, 0b1000); -- assert_eq!(core_simd::Mask::<$type, 4>::from_bitmask(bitmask), mask); - - let values = [true, false]; - let mask = core_simd::Mask::<$type, 2>::from_array(values); - let bitmask = mask.to_bitmask(); - assert_eq!(bitmask, 0b01); -- assert_eq!(core_simd::Mask::<$type, 2>::from_bitmask(bitmask), mask); - } - - #[test] -- 2.25.1 diff --git a/src/intrinsics/simd.rs b/src/intrinsics/simd.rs index a70ced7472f..51fce8c854b 100644 --- a/src/intrinsics/simd.rs +++ b/src/intrinsics/simd.rs @@ -652,6 +652,34 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>( } } + sym::simd_select_bitmask => { + intrinsic_args!(fx, args => (m, a, b); intrinsic); + + if !a.layout().ty.is_simd() { + report_simd_type_validation_error(fx, intrinsic, span, a.layout().ty); + return; + } + assert_eq!(a.layout(), b.layout()); + + let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx); + let lane_layout = fx.layout_of(lane_ty); + + let m = m.load_scalar(fx); + + for lane in 0..lane_count { + let m_lane = fx.bcx.ins().ushr_imm(m, u64::from(lane) as i64); + let m_lane = fx.bcx.ins().band_imm(m_lane, 1); + let a_lane = a.value_lane(fx, lane).load_scalar(fx); + let b_lane = b.value_lane(fx, lane).load_scalar(fx); + + let m_lane = fx.bcx.ins().icmp_imm(IntCC::Equal, m_lane, 0); + let res_lane = + CValue::by_val(fx.bcx.ins().select(m_lane, b_lane, a_lane), lane_layout); + + ret.place_lane(fx, lane).write_cvalue(fx, res_lane); + } + } + sym::simd_bitmask => { intrinsic_args!(fx, args => (a); intrinsic); @@ -748,7 +776,6 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>( // simd_arith_offset // simd_scatter // simd_gather - // simd_select_bitmask _ => { fx.tcx.sess.span_fatal(span, &format!("Unknown SIMD intrinsic {}", intrinsic)); } |