diff options
| -rw-r--r-- | src/intrinsics/llvm_x86.rs | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/intrinsics/llvm_x86.rs b/src/intrinsics/llvm_x86.rs index cd3306f4e56..1615dc5de69 100644 --- a/src/intrinsics/llvm_x86.rs +++ b/src/intrinsics/llvm_x86.rs @@ -170,6 +170,65 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>( } } + "llvm.x86.sse.add.ss" => { + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_ss&ig_expand=171 + intrinsic_args!(fx, args => (a, b); intrinsic); + + assert_eq!(a.layout(), b.layout()); + assert_eq!(a.layout(), ret.layout()); + let layout = a.layout(); + + let (_, lane_ty) = layout.ty.simd_size_and_type(fx.tcx); + assert!(lane_ty.is_floating_point()); + let ret_lane_layout = fx.layout_of(lane_ty); + + ret.write_cvalue(fx, a); + + let a_lane = a.value_lane(fx, 0).load_scalar(fx); + let b_lane = b.value_lane(fx, 0).load_scalar(fx); + + let res = fx.bcx.ins().fadd(a_lane, b_lane); + + let res_lane = CValue::by_val(res, ret_lane_layout); + ret.place_lane(fx, 0).write_cvalue(fx, res_lane); + } + + "llvm.x86.sse.sqrt.ps" => { + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_ps&ig_expand=6245 + intrinsic_args!(fx, args => (a); intrinsic); + + // FIXME use vector instructions when possible + simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| { + fx.bcx.ins().sqrt(lane) + }); + } + + "llvm.x86.sse.max.ps" => { + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_ps&ig_expand=4357 + intrinsic_args!(fx, args => (a, b); intrinsic); + + simd_pair_for_each_lane( + fx, + a, + b, + ret, + &|fx, _lane_ty, _res_lane_ty, a_lane, b_lane| fx.bcx.ins().fmax(a_lane, b_lane), + ); + } + + "llvm.x86.sse.min.ps" => { + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_ps&ig_expand=4489 + intrinsic_args!(fx, args => (a, b); intrinsic); + + simd_pair_for_each_lane( + fx, + a, + b, + ret, + &|fx, _lane_ty, _res_lane_ty, a_lane, b_lane| fx.bcx.ins().fmin(a_lane, b_lane), + ); + } + "llvm.x86.sse.cmp.ps" | "llvm.x86.sse2.cmp.pd" => { let (x, y, kind) = match args { [x, y, kind] => (x, y, kind), |