diff options
| -rw-r--r-- | src/etc/platform-intrinsics/generator.py | 10 | ||||
| -rw-r--r-- | src/etc/platform-intrinsics/powerpc.json | 49 | ||||
| -rw-r--r-- | src/librustc_platform_intrinsics/powerpc.rs | 140 |
3 files changed, 198 insertions, 1 deletions
diff --git a/src/etc/platform-intrinsics/generator.py b/src/etc/platform-intrinsics/generator.py index e3c08bb35e0..e9cf71c32fe 100644 --- a/src/etc/platform-intrinsics/generator.py +++ b/src/etc/platform-intrinsics/generator.py @@ -19,7 +19,7 @@ import itertools SPEC = re.compile( r'^(?:(?P<void>V)|(?P<id>[iusfIUSF])(?:\((?P<start>\d+)-(?P<end>\d+)\)|' r'(?P<width>\d+)(:?/(?P<llvm_width>\d+))?)' - r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMC]*)(?P<force_width>x\d+)?' + r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMCNW]*)(?P<force_width>x\d+)?' r'(?:(?P<pointer>Pm|Pc)(?P<llvm_pointer>/.*)?|(?P<bitcast>->.*))?$' ) @@ -246,6 +246,12 @@ class Vector(Type): return Vector(self._elem, self._length // 2) elif spec == 'd': return Vector(self._elem, self._length * 2) + elif spec == 'N': + elem = self._elem.__class__(self._elem.bitwidth() // 2) + return Vector(elem, self._length * 2) + elif spec == 'W': + elem = self._elem.__class__(self._elem.bitwidth() * 2) + return Vector(elem, self._length // 2) elif spec.startswith('x'): new_bitwidth = int(spec[1:]) return Vector(self._elem, new_bitwidth // self._elem.bitwidth()) @@ -714,6 +720,8 @@ def parse_args(): - 'd': double the length of the vector (u32x2 -> u32x4) - 'n': narrow the element of the vector (u32x4 -> u16x4) - 'w': widen the element of the vector (u16x4 -> u32x4) + - 'N': half the length of the vector element (u32x4 -> u16x8) + - 'W': double the length of the vector element (u16x8 -> u32x4) - 'u': force a number (vector or scalar) to be unsigned int (f32x4 -> u32x4) - 's': force a number (vector or scalar) to be signed int (u32x4 -> i32x4) - 'f': force a number (vector or scalar) to be float (u32x4 -> f32x4) diff --git a/src/etc/platform-intrinsics/powerpc.json b/src/etc/platform-intrinsics/powerpc.json index 7f01aaa3ac1..c70791be030 100644 --- a/src/etc/platform-intrinsics/powerpc.json +++ b/src/etc/platform-intrinsics/powerpc.json @@ -72,6 +72,55 @@ "llvm": "vmin{0.kind}{0.data_type_short}", "ret": "i(8-32)", "args": ["0", "0"] + }, + { + "intrinsic": "sub{0.kind}{0.data_type_short}s", + "width": [128], + "llvm": "vsub{0.kind}{0.data_type_short}s", + "ret": "i(8-32)", + "args": ["0", "0"] + }, + { + "intrinsic": "subc", + "width": [128], + "llvm": "vsubcuw", + "ret": "u32", + "args": ["0", "0"] + }, + { + "intrinsic": "add{0.kind}{0.data_type_short}s", + "width": [128], + "llvm": "vadd{0.kind}{0.data_type_short}s", + "ret": "i(8-32)", + "args": ["0", "0"] + }, + { + "intrinsic": "addc", + "width": [128], + "llvm": "vaddcuw", + "ret": "u32", + "args": ["0", "0"] + }, + { + "intrinsic": "mule{1.kind}{1.data_type_short}", + "width": [128], + "llvm": "vmule{0.kind}{1.data_type_short}", + "ret": "i(16-32)", + "args": ["0N", "1"] + }, + { + "intrinsic": "mulo{1.kind}{1.data_type_short}", + "width": [128], + "llvm": "vmulo{0.kind}{1.data_type_short}", + "ret": "i(16-32)", + "args": ["0N", "1"] + }, + { + "intrinsic": "avg{0.kind}{0.data_type_short}", + "width": [128], + "llvm": "vavg{0.kind}{0.data_type_short}", + "ret": "i(8-32)", + "args": ["0", "0"] } ] } diff --git a/src/librustc_platform_intrinsics/powerpc.rs b/src/librustc_platform_intrinsics/powerpc.rs index 60074cce2b9..b38369665f8 100644 --- a/src/librustc_platform_intrinsics/powerpc.rs +++ b/src/librustc_platform_intrinsics/powerpc.rs @@ -142,6 +142,146 @@ pub fn find(name: &str) -> Option<Intrinsic> { output: &::U32x4, definition: Named("llvm.ppc.altivec.vminuw") }, + "_vec_subsbs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, + output: &::I8x16, + definition: Named("llvm.ppc.altivec.vsubsbs") + }, + "_vec_sububs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, + output: &::U8x16, + definition: Named("llvm.ppc.altivec.vsububs") + }, + "_vec_subshs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, + output: &::I16x8, + definition: Named("llvm.ppc.altivec.vsubshs") + }, + "_vec_subuhs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, + output: &::U16x8, + definition: Named("llvm.ppc.altivec.vsubuhs") + }, + "_vec_subsws" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, + output: &::I32x4, + definition: Named("llvm.ppc.altivec.vsubsws") + }, + "_vec_subuws" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vsubuws") + }, + "_vec_subc" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vsubcuw") + }, + "_vec_addsbs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, + output: &::I8x16, + definition: Named("llvm.ppc.altivec.vaddsbs") + }, + "_vec_addubs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, + output: &::U8x16, + definition: Named("llvm.ppc.altivec.vaddubs") + }, + "_vec_addshs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, + output: &::I16x8, + definition: Named("llvm.ppc.altivec.vaddshs") + }, + "_vec_adduhs" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, + output: &::U16x8, + definition: Named("llvm.ppc.altivec.vadduhs") + }, + "_vec_addsws" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, + output: &::I32x4, + definition: Named("llvm.ppc.altivec.vaddsws") + }, + "_vec_adduws" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vadduws") + }, + "_vec_addc" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vaddcuw") + }, + "_vec_mulesb" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, + output: &::I16x8, + definition: Named("llvm.ppc.altivec.vmulesb") + }, + "_vec_muleub" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, + output: &::U16x8, + definition: Named("llvm.ppc.altivec.vmuleub") + }, + "_vec_mulesh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, + output: &::I32x4, + definition: Named("llvm.ppc.altivec.vmulesh") + }, + "_vec_muleuh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vmuleuh") + }, + "_vec_mulosb" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, + output: &::I16x8, + definition: Named("llvm.ppc.altivec.vmulosb") + }, + "_vec_muloub" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, + output: &::U16x8, + definition: Named("llvm.ppc.altivec.vmuloub") + }, + "_vec_mulosh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, + output: &::I32x4, + definition: Named("llvm.ppc.altivec.vmulosh") + }, + "_vec_mulouh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vmulouh") + }, + "_vec_avgsb" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, + output: &::I8x16, + definition: Named("llvm.ppc.altivec.vavgsb") + }, + "_vec_avgub" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, + output: &::U8x16, + definition: Named("llvm.ppc.altivec.vavgub") + }, + "_vec_avgsh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, + output: &::I16x8, + definition: Named("llvm.ppc.altivec.vavgsh") + }, + "_vec_avguh" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, + output: &::U16x8, + definition: Named("llvm.ppc.altivec.vavguh") + }, + "_vec_avgsw" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, + output: &::I32x4, + definition: Named("llvm.ppc.altivec.vavgsw") + }, + "_vec_avguw" => Intrinsic { + inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, + output: &::U32x4, + definition: Named("llvm.ppc.altivec.vavguw") + }, _ => return None, }) } |