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-rw-r--r--library/core/src/intrinsics/mod.rs2
-rw-r--r--library/core/src/num/uint_macros.rs10
2 files changed, 5 insertions, 7 deletions
diff --git a/library/core/src/intrinsics/mod.rs b/library/core/src/intrinsics/mod.rs
index c505eb95013..8db390622ba 100644
--- a/library/core/src/intrinsics/mod.rs
+++ b/library/core/src/intrinsics/mod.rs
@@ -3247,7 +3247,7 @@ pub const fn three_way_compare<T: Copy>(_lhs: T, _rhss: T) -> crate::cmp::Orderi
 /// Combine two values which have no bits in common.
 ///
 /// This allows the backend to implement it as `a + b` *or* `a | b`,
-/// depending which us easier to implement on a specific target.
+/// depending which is easier to implement on a specific target.
 ///
 /// # Safety
 ///
diff --git a/library/core/src/num/uint_macros.rs b/library/core/src/num/uint_macros.rs
index f2d41fd93d5..29f6791ee6a 100644
--- a/library/core/src/num/uint_macros.rs
+++ b/library/core/src/num/uint_macros.rs
@@ -1187,13 +1187,11 @@ macro_rules! uint_impl {
             self % rhs
         }
 
-        /// Same value as
-        #[doc = concat!("`<", stringify!($SelfT), " as BitOr>::bitor(self, other)`")]
-        /// but UB if any bit position is set in both inputs.
+        /// Same value as `self | other`, but UB if any bit position is set in both inputs.
         ///
-        /// This is a situational μoptimization for places where you'd rather use
-        /// addition on some platforms and bitwise or on other platforms, based on
-        /// exactly which instructions combine better with whatever else you're
+        /// This is a situational micro-optimization for places where you'd rather
+        /// use addition on some platforms and bitwise or on other platforms, based
+        /// on exactly which instructions combine better with whatever else you're
         /// doing.  Note that there's no reason to bother using this for places
         /// where it's clear from the operations involved that they can't overlap.
         /// For example, if you're combining `u16`s into a `u32` with