diff options
| -rw-r--r-- | .gitignore | 2 | ||||
| -rw-r--r-- | src/intrinsic/archs.rs | 1336 | ||||
| -rw-r--r-- | tools/generate_intrinsics.py | 229 |
3 files changed, 1556 insertions, 11 deletions
diff --git a/.gitignore b/.gitignore index 0b611d05b5c..ffd36ddb7db 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,5 @@ res test-backend gcc_path benchmarks +tools/llvm-project +tools/llvmint diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index ef8a54f3530..bfeb30f2913 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,3 +1,5 @@ +// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` +// DO NOT EDIT IT! match name { // AMDGPU "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", @@ -32,13 +34,122 @@ match name { "llvm.aarch64.dmb" => "__builtin_arm_dmb", "llvm.aarch64.dsb" => "__builtin_arm_dsb", "llvm.aarch64.isb" => "__builtin_arm_isb", + "llvm.aarch64.sve.aesd" => "__builtin_sve_svaesd_u8", + "llvm.aarch64.sve.aese" => "__builtin_sve_svaese_u8", + "llvm.aarch64.sve.aesimc" => "__builtin_sve_svaesimc_u8", + "llvm.aarch64.sve.aesmc" => "__builtin_sve_svaesmc_u8", + "llvm.aarch64.sve.rax1" => "__builtin_sve_svrax1_u64", + "llvm.aarch64.sve.rdffr" => "__builtin_sve_svrdffr", + "llvm.aarch64.sve.rdffr.z" => "__builtin_sve_svrdffr_z", + "llvm.aarch64.sve.setffr" => "__builtin_sve_svsetffr", + "llvm.aarch64.sve.sm4e" => "__builtin_sve_svsm4e_u32", + "llvm.aarch64.sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32", + "llvm.aarch64.sve.wrffr" => "__builtin_sve_svwrffr", + "llvm.aarch64.tcancel" => "__builtin_arm_tcancel", + "llvm.aarch64.tcommit" => "__builtin_arm_tcommit", + "llvm.aarch64.tstart" => "__builtin_arm_tstart", + "llvm.aarch64.ttest" => "__builtin_arm_ttest", + // amdgcn + "llvm.amdgcn.alignbyte" => "__builtin_amdgcn_alignbyte", + "llvm.amdgcn.buffer.wbinvl1" => "__builtin_amdgcn_buffer_wbinvl1", + "llvm.amdgcn.buffer.wbinvl1.sc" => "__builtin_amdgcn_buffer_wbinvl1_sc", + "llvm.amdgcn.buffer.wbinvl1.vol" => "__builtin_amdgcn_buffer_wbinvl1_vol", + "llvm.amdgcn.cubeid" => "__builtin_amdgcn_cubeid", + "llvm.amdgcn.cubema" => "__builtin_amdgcn_cubema", + "llvm.amdgcn.cubesc" => "__builtin_amdgcn_cubesc", + "llvm.amdgcn.cubetc" => "__builtin_amdgcn_cubetc", + "llvm.amdgcn.cvt.pk.i16" => "__builtin_amdgcn_cvt_pk_i16", + "llvm.amdgcn.cvt.pk.u16" => "__builtin_amdgcn_cvt_pk_u16", + "llvm.amdgcn.cvt.pk.u8.f32" => "__builtin_amdgcn_cvt_pk_u8_f32", + "llvm.amdgcn.cvt.pknorm.i16" => "__builtin_amdgcn_cvt_pknorm_i16", + "llvm.amdgcn.cvt.pknorm.u16" => "__builtin_amdgcn_cvt_pknorm_u16", + "llvm.amdgcn.cvt.pkrtz" => "__builtin_amdgcn_cvt_pkrtz", + "llvm.amdgcn.dispatch.id" => "__builtin_amdgcn_dispatch_id", + "llvm.amdgcn.ds.bpermute" => "__builtin_amdgcn_ds_bpermute", + "llvm.amdgcn.ds.fadd.v2bf16" => "__builtin_amdgcn_ds_atomic_fadd_v2bf16", + "llvm.amdgcn.ds.gws.barrier" => "__builtin_amdgcn_ds_gws_barrier", + "llvm.amdgcn.ds.gws.init" => "__builtin_amdgcn_ds_gws_init", + "llvm.amdgcn.ds.gws.sema.br" => "__builtin_amdgcn_ds_gws_sema_br", + "llvm.amdgcn.ds.gws.sema.p" => "__builtin_amdgcn_ds_gws_sema_p", + "llvm.amdgcn.ds.gws.sema.release.all" => "__builtin_amdgcn_ds_gws_sema_release_all", + "llvm.amdgcn.ds.gws.sema.v" => "__builtin_amdgcn_ds_gws_sema_v", + "llvm.amdgcn.ds.permute" => "__builtin_amdgcn_ds_permute", + "llvm.amdgcn.ds.swizzle" => "__builtin_amdgcn_ds_swizzle", + "llvm.amdgcn.endpgm" => "__builtin_amdgcn_endpgm", + "llvm.amdgcn.fdot2" => "__builtin_amdgcn_fdot2", + "llvm.amdgcn.fmed3" => "__builtin_amdgcn_fmed3", + "llvm.amdgcn.fmul.legacy" => "__builtin_amdgcn_fmul_legacy", + "llvm.amdgcn.groupstaticsize" => "__builtin_amdgcn_groupstaticsize", + "llvm.amdgcn.implicit.buffer.ptr" => "__builtin_amdgcn_implicit_buffer_ptr", + "llvm.amdgcn.implicitarg.ptr" => "__builtin_amdgcn_implicitarg_ptr", + "llvm.amdgcn.interp.mov" => "__builtin_amdgcn_interp_mov", + "llvm.amdgcn.interp.p1" => "__builtin_amdgcn_interp_p1", + "llvm.amdgcn.interp.p1.f16" => "__builtin_amdgcn_interp_p1_f16", + "llvm.amdgcn.interp.p2" => "__builtin_amdgcn_interp_p2", + "llvm.amdgcn.interp.p2.f16" => "__builtin_amdgcn_interp_p2_f16", + "llvm.amdgcn.is.private" => "__builtin_amdgcn_is_private", + "llvm.amdgcn.is.shared" => "__builtin_amdgcn_is_shared", + "llvm.amdgcn.kernarg.segment.ptr" => "__builtin_amdgcn_kernarg_segment_ptr", + "llvm.amdgcn.lerp" => "__builtin_amdgcn_lerp", + "llvm.amdgcn.mbcnt.hi" => "__builtin_amdgcn_mbcnt_hi", + "llvm.amdgcn.mbcnt.lo" => "__builtin_amdgcn_mbcnt_lo", + "llvm.amdgcn.mqsad.pk.u16.u8" => "__builtin_amdgcn_mqsad_pk_u16_u8", + "llvm.amdgcn.mqsad.u32.u8" => "__builtin_amdgcn_mqsad_u32_u8", + "llvm.amdgcn.msad.u8" => "__builtin_amdgcn_msad_u8", + "llvm.amdgcn.perm" => "__builtin_amdgcn_perm", + "llvm.amdgcn.permlane16" => "__builtin_amdgcn_permlane16", + "llvm.amdgcn.permlanex16" => "__builtin_amdgcn_permlanex16", + "llvm.amdgcn.qsad.pk.u16.u8" => "__builtin_amdgcn_qsad_pk_u16_u8", + "llvm.amdgcn.queue.ptr" => "__builtin_amdgcn_queue_ptr", + "llvm.amdgcn.rcp.legacy" => "__builtin_amdgcn_rcp_legacy", + "llvm.amdgcn.readfirstlane" => "__builtin_amdgcn_readfirstlane", + "llvm.amdgcn.readlane" => "__builtin_amdgcn_readlane", + "llvm.amdgcn.rsq.legacy" => "__builtin_amdgcn_rsq_legacy", + "llvm.amdgcn.s.barrier" => "__builtin_amdgcn_s_barrier", + "llvm.amdgcn.s.dcache.inv" => "__builtin_amdgcn_s_dcache_inv", + "llvm.amdgcn.s.dcache.inv.vol" => "__builtin_amdgcn_s_dcache_inv_vol", + "llvm.amdgcn.s.dcache.wb" => "__builtin_amdgcn_s_dcache_wb", + "llvm.amdgcn.s.dcache.wb.vol" => "__builtin_amdgcn_s_dcache_wb_vol", + "llvm.amdgcn.s.decperflevel" => "__builtin_amdgcn_s_decperflevel", + "llvm.amdgcn.s.get.waveid.in.workgroup" => "__builtin_amdgcn_s_get_waveid_in_workgroup", + "llvm.amdgcn.s.getpc" => "__builtin_amdgcn_s_getpc", + "llvm.amdgcn.s.getreg" => "__builtin_amdgcn_s_getreg", + "llvm.amdgcn.s.incperflevel" => "__builtin_amdgcn_s_incperflevel", + "llvm.amdgcn.s.memrealtime" => "__builtin_amdgcn_s_memrealtime", + "llvm.amdgcn.s.memtime" => "__builtin_amdgcn_s_memtime", + "llvm.amdgcn.s.sendmsg" => "__builtin_amdgcn_s_sendmsg", + "llvm.amdgcn.s.sendmsghalt" => "__builtin_amdgcn_s_sendmsghalt", + "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", + "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", + "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", + "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", + "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", + "llvm.amdgcn.sad.u8" => "__builtin_amdgcn_sad_u8", + "llvm.amdgcn.sdot2" => "__builtin_amdgcn_sdot2", + "llvm.amdgcn.sdot4" => "__builtin_amdgcn_sdot4", + "llvm.amdgcn.sdot8" => "__builtin_amdgcn_sdot8", + "llvm.amdgcn.udot2" => "__builtin_amdgcn_udot2", + "llvm.amdgcn.udot4" => "__builtin_amdgcn_udot4", + "llvm.amdgcn.udot8" => "__builtin_amdgcn_udot8", + "llvm.amdgcn.wave.barrier" => "__builtin_amdgcn_wave_barrier", + "llvm.amdgcn.wavefrontsize" => "__builtin_amdgcn_wavefrontsize", + "llvm.amdgcn.writelane" => "__builtin_amdgcn_writelane", // arm "llvm.arm.cdp" => "__builtin_arm_cdp", "llvm.arm.cdp2" => "__builtin_arm_cdp2", + "llvm.arm.cmse.tt" => "__builtin_arm_cmse_TT", + "llvm.arm.cmse.tta" => "__builtin_arm_cmse_TTA", + "llvm.arm.cmse.ttat" => "__builtin_arm_cmse_TTAT", + "llvm.arm.cmse.ttt" => "__builtin_arm_cmse_TTT", "llvm.arm.dmb" => "__builtin_arm_dmb", "llvm.arm.dsb" => "__builtin_arm_dsb", "llvm.arm.get.fpscr" => "__builtin_arm_get_fpscr", "llvm.arm.isb" => "__builtin_arm_isb", + "llvm.arm.ldc" => "__builtin_arm_ldc", + "llvm.arm.ldc2" => "__builtin_arm_ldc2", + "llvm.arm.ldc2l" => "__builtin_arm_ldc2l", + "llvm.arm.ldcl" => "__builtin_arm_ldcl", "llvm.arm.mcr" => "__builtin_arm_mcr", "llvm.arm.mcr2" => "__builtin_arm_mcr2", "llvm.arm.mcrr" => "__builtin_arm_mcrr", @@ -46,11 +157,95 @@ match name { "llvm.arm.mrc" => "__builtin_arm_mrc", "llvm.arm.mrc2" => "__builtin_arm_mrc2", "llvm.arm.qadd" => "__builtin_arm_qadd", + "llvm.arm.qadd16" => "__builtin_arm_qadd16", + "llvm.arm.qadd8" => "__builtin_arm_qadd8", + "llvm.arm.qasx" => "__builtin_arm_qasx", + "llvm.arm.qsax" => "__builtin_arm_qsax", "llvm.arm.qsub" => "__builtin_arm_qsub", + "llvm.arm.qsub16" => "__builtin_arm_qsub16", + "llvm.arm.qsub8" => "__builtin_arm_qsub8", + "llvm.arm.sadd16" => "__builtin_arm_sadd16", + "llvm.arm.sadd8" => "__builtin_arm_sadd8", + "llvm.arm.sasx" => "__builtin_arm_sasx", + "llvm.arm.sel" => "__builtin_arm_sel", "llvm.arm.set.fpscr" => "__builtin_arm_set_fpscr", + "llvm.arm.shadd16" => "__builtin_arm_shadd16", + "llvm.arm.shadd8" => "__builtin_arm_shadd8", + "llvm.arm.shasx" => "__builtin_arm_shasx", + "llvm.arm.shsax" => "__builtin_arm_shsax", + "llvm.arm.shsub16" => "__builtin_arm_shsub16", + "llvm.arm.shsub8" => "__builtin_arm_shsub8", + "llvm.arm.smlabb" => "__builtin_arm_smlabb", + "llvm.arm.smlabt" => "__builtin_arm_smlabt", + "llvm.arm.smlad" => "__builtin_arm_smlad", + "llvm.arm.smladx" => "__builtin_arm_smladx", + "llvm.arm.smlald" => "__builtin_arm_smlald", + "llvm.arm.smlaldx" => "__builtin_arm_smlaldx", + "llvm.arm.smlatb" => "__builtin_arm_smlatb", + "llvm.arm.smlatt" => "__builtin_arm_smlatt", + "llvm.arm.smlawb" => "__builtin_arm_smlawb", + "llvm.arm.smlawt" => "__builtin_arm_smlawt", + "llvm.arm.smlsd" => "__builtin_arm_smlsd", + "llvm.arm.smlsdx" => "__builtin_arm_smlsdx", + "llvm.arm.smlsld" => "__builtin_arm_smlsld", + "llvm.arm.smlsldx" => "__builtin_arm_smlsldx", + "llvm.arm.smuad" => "__builtin_arm_smuad", + "llvm.arm.smuadx" => "__builtin_arm_smuadx", + "llvm.arm.smulbb" => "__builtin_arm_smulbb", + "llvm.arm.smulbt" => "__builtin_arm_smulbt", + "llvm.arm.smultb" => "__builtin_arm_smultb", + "llvm.arm.smultt" => "__builtin_arm_smultt", + "llvm.arm.smulwb" => "__builtin_arm_smulwb", + "llvm.arm.smulwt" => "__builtin_arm_smulwt", + "llvm.arm.smusd" => "__builtin_arm_smusd", + "llvm.arm.smusdx" => "__builtin_arm_smusdx", "llvm.arm.ssat" => "__builtin_arm_ssat", + "llvm.arm.ssat16" => "__builtin_arm_ssat16", + "llvm.arm.ssax" => "__builtin_arm_ssax", + "llvm.arm.ssub16" => "__builtin_arm_ssub16", + "llvm.arm.ssub8" => "__builtin_arm_ssub8", + "llvm.arm.stc" => "__builtin_arm_stc", + "llvm.arm.stc2" => "__builtin_arm_stc2", + "llvm.arm.stc2l" => "__builtin_arm_stc2l", + "llvm.arm.stcl" => "__builtin_arm_stcl", + "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", + "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", "llvm.arm.thread.pointer" => "__builtin_thread_pointer", + "llvm.arm.uadd16" => "__builtin_arm_uadd16", + "llvm.arm.uadd8" => "__builtin_arm_uadd8", + "llvm.arm.uasx" => "__builtin_arm_uasx", + "llvm.arm.uhadd16" => "__builtin_arm_uhadd16", + "llvm.arm.uhadd8" => "__builtin_arm_uhadd8", + "llvm.arm.uhasx" => "__builtin_arm_uhasx", + "llvm.arm.uhsax" => "__builtin_arm_uhsax", + "llvm.arm.uhsub16" => "__builtin_arm_uhsub16", + "llvm.arm.uhsub8" => "__builtin_arm_uhsub8", + "llvm.arm.uqadd16" => "__builtin_arm_uqadd16", + "llvm.arm.uqadd8" => "__builtin_arm_uqadd8", + "llvm.arm.uqasx" => "__builtin_arm_uqasx", + "llvm.arm.uqsax" => "__builtin_arm_uqsax", + "llvm.arm.uqsub16" => "__builtin_arm_uqsub16", + "llvm.arm.uqsub8" => "__builtin_arm_uqsub8", + "llvm.arm.usad8" => "__builtin_arm_usad8", + "llvm.arm.usada8" => "__builtin_arm_usada8", "llvm.arm.usat" => "__builtin_arm_usat", + "llvm.arm.usat16" => "__builtin_arm_usat16", + "llvm.arm.usax" => "__builtin_arm_usax", + "llvm.arm.usub16" => "__builtin_arm_usub16", + "llvm.arm.usub8" => "__builtin_arm_usub8", + "llvm.arm.uxtab16" => "__builtin_arm_uxtab16", + "llvm.arm.uxtb16" => "__builtin_arm_uxtb16", + // bpf + "llvm.bpf.btf.type.id" => "__builtin_bpf_btf_type_id", + "llvm.bpf.compare" => "__builtin_bpf_compare", + "llvm.bpf.load.byte" => "__builtin_bpf_load_byte", + "llvm.bpf.load.half" => "__builtin_bpf_load_half", + "llvm.bpf.load.word" => "__builtin_bpf_load_word", + "llvm.bpf.passthrough" => "__builtin_bpf_passthrough", + "llvm.bpf.preserve.enum.value" => "__builtin_bpf_preserve_enum_value", + "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", + "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", + "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", // cuda "llvm.cuda.syncthreads" => "__syncthreads", // hexagon @@ -908,10 +1103,20 @@ match name { "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", // mips + "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", + "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", + "llvm.mips.absq.s.w" => "__builtin_mips_absq_s_w", "llvm.mips.add.a.b" => "__builtin_msa_add_a_b", "llvm.mips.add.a.d" => "__builtin_msa_add_a_d", "llvm.mips.add.a.h" => "__builtin_msa_add_a_h", "llvm.mips.add.a.w" => "__builtin_msa_add_a_w", + "llvm.mips.addq.ph" => "__builtin_mips_addq_ph", + "llvm.mips.addq.s.ph" => "__builtin_mips_addq_s_ph", + "llvm.mips.addq.s.w" => "__builtin_mips_addq_s_w", + "llvm.mips.addqh.ph" => "__builtin_mips_addqh_ph", + "llvm.mips.addqh.r.ph" => "__builtin_mips_addqh_r_ph", + "llvm.mips.addqh.r.w" => "__builtin_mips_addqh_r_w", + "llvm.mips.addqh.w" => "__builtin_mips_addqh_w", "llvm.mips.adds.a.b" => "__builtin_msa_adds_a_b", "llvm.mips.adds.a.d" => "__builtin_msa_adds_a_d", "llvm.mips.adds.a.h" => "__builtin_msa_adds_a_h", @@ -1067,6 +1272,9 @@ match name { "llvm.mips.clti.u.d" => "__builtin_msa_clti_u_d", "llvm.mips.clti.u.h" => "__builtin_msa_clti_u_h", "llvm.mips.clti.u.w" => "__builtin_msa_clti_u_w", + "llvm.mips.cmp.eq.ph" => "__builtin_mips_cmp_eq_ph", + "llvm.mips.cmp.le.ph" => "__builtin_mips_cmp_le_ph", + "llvm.mips.cmp.lt.ph" => "__builtin_mips_cmp_lt_ph", "llvm.mips.cmpgdu.eq.qb" => "__builtin_mips_cmpgdu_eq_qb", "llvm.mips.cmpgdu.le.qb" => "__builtin_mips_cmpgdu_le_qb", "llvm.mips.cmpgdu.lt.qb" => "__builtin_mips_cmpgdu_lt_qb", @@ -1107,10 +1315,18 @@ match name { "llvm.mips.dpadd.u.d" => "__builtin_msa_dpadd_u_d", "llvm.mips.dpadd.u.h" => "__builtin_msa_dpadd_u_h", "llvm.mips.dpadd.u.w" => "__builtin_msa_dpadd_u_w", + "llvm.mips.dpaq.s.w.ph" => "__builtin_mips_dpaq_s_w_ph", + "llvm.mips.dpaq.sa.l.w" => "__builtin_mips_dpaq_sa_l_w", + "llvm.mips.dpaqx.s.w.ph" => "__builtin_mips_dpaqx_s_w_ph", + "llvm.mips.dpaqx.sa.w.ph" => "__builtin_mips_dpaqx_sa_w_ph", "llvm.mips.dpau.h.qbl" => "__builtin_mips_dpau_h_qbl", "llvm.mips.dpau.h.qbr" => "__builtin_mips_dpau_h_qbr", "llvm.mips.dpax.w.ph" => "__builtin_mips_dpax_w_ph", "llvm.mips.dps.w.ph" => "__builtin_mips_dps_w_ph", + "llvm.mips.dpsq.s.w.ph" => "__builtin_mips_dpsq_s_w_ph", + "llvm.mips.dpsq.sa.l.w" => "__builtin_mips_dpsq_sa_l_w", + "llvm.mips.dpsqx.s.w.ph" => "__builtin_mips_dpsqx_s_w_ph", + "llvm.mips.dpsqx.sa.w.ph" => "__builtin_mips_dpsqx_sa_w_ph", "llvm.mips.dpsu.h.qbl" => "__builtin_mips_dpsu_h_qbl", "llvm.mips.dpsu.h.qbr" => "__builtin_mips_dpsu_h_qbr", "llvm.mips.dpsub.s.d" => "__builtin_msa_dpsub_s_d", @@ -1154,11 +1370,14 @@ match name { "llvm.mips.fcune.w" => "__builtin_msa_fcune_w", "llvm.mips.fdiv.d" => "__builtin_msa_fdiv_d", "llvm.mips.fdiv.w" => "__builtin_msa_fdiv_w", + "llvm.mips.fexdo.h" => "__builtin_msa_fexdo_h", "llvm.mips.fexdo.w" => "__builtin_msa_fexdo_w", "llvm.mips.fexp2.d" => "__builtin_msa_fexp2_d", "llvm.mips.fexp2.w" => "__builtin_msa_fexp2_w", "llvm.mips.fexupl.d" => "__builtin_msa_fexupl_d", + "llvm.mips.fexupl.w" => "__builtin_msa_fexupl_w", "llvm.mips.fexupr.d" => "__builtin_msa_fexupr_d", + "llvm.mips.fexupr.w" => "__builtin_msa_fexupr_w", "llvm.mips.ffint.s.d" => "__builtin_msa_ffint_s_d", "llvm.mips.ffint.s.w" => "__builtin_msa_ffint_s_w", "llvm.mips.ffint.u.d" => "__builtin_msa_ffint_u_d", @@ -1275,6 +1494,8 @@ match name { "llvm.mips.ldi.d" => "__builtin_msa_ldi_d", "llvm.mips.ldi.h" => "__builtin_msa_ldi_h", "llvm.mips.ldi.w" => "__builtin_msa_ldi_w", + "llvm.mips.ldr.d" => "__builtin_msa_ldr_d", + "llvm.mips.ldr.w" => "__builtin_msa_ldr_w", "llvm.mips.lhx" => "__builtin_mips_lhx", "llvm.mips.lsa" => "__builtin_mips_lsa", "llvm.mips.lwx" => "__builtin_mips_lwx", @@ -1288,6 +1509,10 @@ match name { "llvm.mips.maddv.d" => "__builtin_msa_maddv_d", "llvm.mips.maddv.h" => "__builtin_msa_maddv_h", "llvm.mips.maddv.w" => "__builtin_msa_maddv_w", + "llvm.mips.maq.s.w.phl" => "__builtin_mips_maq_s_w_phl", + "llvm.mips.maq.s.w.phr" => "__builtin_mips_maq_s_w_phr", + "llvm.mips.maq.sa.w.phl" => "__builtin_mips_maq_sa_w_phl", + "llvm.mips.maq.sa.w.phr" => "__builtin_mips_maq_sa_w_phr", "llvm.mips.max.a.b" => "__builtin_msa_max_a_b", "llvm.mips.max.a.d" => "__builtin_msa_max_a_d", "llvm.mips.max.a.h" => "__builtin_msa_max_a_h", @@ -1353,9 +1578,18 @@ match name { "llvm.mips.mul.q.h" => "__builtin_msa_mul_q_h", "llvm.mips.mul.q.w" => "__builtin_msa_mul_q_w", "llvm.mips.mul.s.ph" => "__builtin_mips_mul_s_ph", + "llvm.mips.muleq.s.w.phl" => "__builtin_mips_muleq_s_w_phl", + "llvm.mips.muleq.s.w.phr" => "__builtin_mips_muleq_s_w_phr", + "llvm.mips.muleu.s.ph.qbl" => "__builtin_mips_muleu_s_ph_qbl", + "llvm.mips.muleu.s.ph.qbr" => "__builtin_mips_muleu_s_ph_qbr", + "llvm.mips.mulq.rs.ph" => "__builtin_mips_mulq_rs_ph", + "llvm.mips.mulq.rs.w" => "__builtin_mips_mulq_rs_w", + "llvm.mips.mulq.s.ph" => "__builtin_mips_mulq_s_ph", + "llvm.mips.mulq.s.w" => "__builtin_mips_mulq_s_w", "llvm.mips.mulr.q.h" => "__builtin_msa_mulr_q_h", "llvm.mips.mulr.q.w" => "__builtin_msa_mulr_q_w", "llvm.mips.mulsa.w.ph" => "__builtin_mips_mulsa_w_ph", + "llvm.mips.mulsaq.s.w.ph" => "__builtin_mips_mulsaq_s_w_ph", "llvm.mips.mult" => "__builtin_mips_mult", "llvm.mips.multu" => "__builtin_mips_multu", "llvm.mips.mulv.b" => "__builtin_msa_mulv_b", @@ -1374,6 +1608,7 @@ match name { "llvm.mips.nori.b" => "__builtin_msa_nori_b", "llvm.mips.or.v" => "__builtin_msa_or_v", "llvm.mips.ori.b" => "__builtin_msa_ori_b", + "llvm.mips.packrl.ph" => "__builtin_mips_packrl_ph", "llvm.mips.pckev.b" => "__builtin_msa_pckev_b", "llvm.mips.pckev.d" => "__builtin_msa_pckev_d", "llvm.mips.pckev.h" => "__builtin_msa_pckev_h", @@ -1386,13 +1621,29 @@ match name { "llvm.mips.pcnt.d" => "__builtin_msa_pcnt_d", "llvm.mips.pcnt.h" => "__builtin_msa_pcnt_h", "llvm.mips.pcnt.w" => "__builtin_msa_pcnt_w", + "llvm.mips.pick.ph" => "__builtin_mips_pick_ph", "llvm.mips.pick.qb" => "__builtin_mips_pick_qb", + "llvm.mips.preceq.w.phl" => "__builtin_mips_preceq_w_phl", + "llvm.mips.preceq.w.phr" => "__builtin_mips_preceq_w_phr", + "llvm.mips.precequ.ph.qbl" => "__builtin_mips_precequ_ph_qbl", + "llvm.mips.precequ.ph.qbla" => "__builtin_mips_precequ_ph_qbla", + "llvm.mips.precequ.ph.qbr" => "__builtin_mips_precequ_ph_qbr", + "llvm.mips.precequ.ph.qbra" => "__builtin_mips_precequ_ph_qbra", + "llvm.mips.preceu.ph.qbl" => "__builtin_mips_preceu_ph_qbl", + "llvm.mips.preceu.ph.qbla" => "__builtin_mips_preceu_ph_qbla", + "llvm.mips.preceu.ph.qbr" => "__builtin_mips_preceu_ph_qbr", + "llvm.mips.preceu.ph.qbra" => "__builtin_mips_preceu_ph_qbra", "llvm.mips.precr.qb.ph" => "__builtin_mips_precr_qb_ph", "llvm.mips.precr.sra.ph.w" => "__builtin_mips_precr_sra_ph_w", "llvm.mips.precr.sra.r.ph.w" => "__builtin_mips_precr_sra_r_ph_w", + "llvm.mips.precrq.ph.w" => "__builtin_mips_precrq_ph_w", + "llvm.mips.precrq.qb.ph" => "__builtin_mips_precrq_qb_ph", + "llvm.mips.precrq.rs.ph.w" => "__builtin_mips_precrq_rs_ph_w", + "llvm.mips.precrqu.s.qb.ph" => "__builtin_mips_precrqu_s_qb_ph", "llvm.mips.prepend" => "__builtin_mips_prepend", "llvm.mips.raddu.w.qb" => "__builtin_mips_raddu_w_qb", "llvm.mips.rddsp" => "__builtin_mips_rddsp", + "llvm.mips.repl.ph" => "__builtin_mips_repl_ph", "llvm.mips.repl.qb" => "__builtin_mips_repl_qb", "llvm.mips.sat.s.b" => "__builtin_msa_sat_s_b", "llvm.mips.sat.s.d" => "__builtin_msa_sat_s_d", @@ -1406,9 +1657,15 @@ match name { "llvm.mips.shf.h" => "__builtin_msa_shf_h", "llvm.mips.shf.w" => "__builtin_msa_shf_w", "llvm.mips.shilo" => "__builtin_mips_shilo", + "llvm.mips.shll.ph" => "__builtin_mips_shll_ph", "llvm.mips.shll.qb" => "__builtin_mips_shll_qb", + "llvm.mips.shll.s.ph" => "__builtin_mips_shll_s_ph", + "llvm.mips.shll.s.w" => "__builtin_mips_shll_s_w", + "llvm.mips.shra.ph" => "__builtin_mips_shra_ph", "llvm.mips.shra.qb" => "__builtin_mips_shra_qb", + "llvm.mips.shra.r.ph" => "__builtin_mips_shra_r_ph", "llvm.mips.shra.r.qb" => "__builtin_mips_shra_r_qb", + "llvm.mips.shra.r.w" => "__builtin_mips_shra_r_w", "llvm.mips.shrl.ph" => "__builtin_mips_shrl_ph", "llvm.mips.shrl.qb" => "__builtin_mips_shrl_qb", "llvm.mips.sld.b" => "__builtin_msa_sld_b", @@ -1471,6 +1728,15 @@ match name { "llvm.mips.st.d" => "__builtin_msa_st_d", "llvm.mips.st.h" => "__builtin_msa_st_h", "llvm.mips.st.w" => "__builtin_msa_st_w", + "llvm.mips.str.d" => "__builtin_msa_str_d", + "llvm.mips.str.w" => "__builtin_msa_str_w", + "llvm.mips.subq.ph" => "__builtin_mips_subq_ph", + "llvm.mips.subq.s.ph" => "__builtin_mips_subq_s_ph", + "llvm.mips.subq.s.w" => "__builtin_mips_subq_s_w", + "llvm.mips.subqh.ph" => "__builtin_mips_subqh_ph", + "llvm.mips.subqh.r.ph" => "__builtin_mips_subqh_r_ph", + "llvm.mips.subqh.r.w" => "__builtin_mips_subqh_r_w", + "llvm.mips.subqh.w" => "__builtin_mips_subqh_w", "llvm.mips.subs.s.b" => "__builtin_msa_subs_s_b", "llvm.mips.subs.s.d" => "__builtin_msa_subs_s_d", "llvm.mips.subs.s.h" => "__builtin_msa_subs_s_h", @@ -2035,6 +2301,13 @@ match name { "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", // ppc + "llvm.ppc.addex" => "__builtin_ppc_addex", + "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", + "llvm.ppc.altivec.crypto.vpermxor" => "__builtin_altivec_crypto_vpermxor", + "llvm.ppc.altivec.crypto.vpermxor.be" => "__builtin_altivec_crypto_vpermxor_be", + "llvm.ppc.altivec.crypto.vsbox" => "__builtin_altivec_crypto_vsbox", + "llvm.ppc.altivec.crypto.vshasigmad" => "__builtin_altivec_crypto_vshasigmad", + "llvm.ppc.altivec.crypto.vshasigmaw" => "__builtin_altivec_crypto_vshasigmaw", "llvm.ppc.altivec.dss" => "__builtin_altivec_dss", "llvm.ppc.altivec.dssall" => "__builtin_altivec_dssall", "llvm.ppc.altivec.dst" => "__builtin_altivec_dst", @@ -2043,7 +2316,14 @@ match name { "llvm.ppc.altivec.dstt" => "__builtin_altivec_dstt", "llvm.ppc.altivec.mfvscr" => "__builtin_altivec_mfvscr", "llvm.ppc.altivec.mtvscr" => "__builtin_altivec_mtvscr", + "llvm.ppc.altivec.mtvsrbm" => "__builtin_altivec_mtvsrbm", + "llvm.ppc.altivec.mtvsrdm" => "__builtin_altivec_mtvsrdm", + "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", + "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", + "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", + "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", + "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", @@ -2056,16 +2336,27 @@ match name { "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", + "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd", + "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq", "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", + "llvm.ppc.altivec.vcfuged" => "__builtin_altivec_vcfuged", "llvm.ppc.altivec.vcfux" => "__builtin_altivec_vcfux", + "llvm.ppc.altivec.vclrlb" => "__builtin_altivec_vclrlb", + "llvm.ppc.altivec.vclrrb" => "__builtin_altivec_vclrrb", + "llvm.ppc.altivec.vclzdm" => "__builtin_altivec_vclzdm", + "llvm.ppc.altivec.vclzlsbb" => "__builtin_altivec_vclzlsbb", "llvm.ppc.altivec.vcmpbfp" => "__builtin_altivec_vcmpbfp", "llvm.ppc.altivec.vcmpbfp.p" => "__builtin_altivec_vcmpbfp_p", "llvm.ppc.altivec.vcmpeqfp" => "__builtin_altivec_vcmpeqfp", "llvm.ppc.altivec.vcmpeqfp.p" => "__builtin_altivec_vcmpeqfp_p", "llvm.ppc.altivec.vcmpequb" => "__builtin_altivec_vcmpequb", "llvm.ppc.altivec.vcmpequb.p" => "__builtin_altivec_vcmpequb_p", + "llvm.ppc.altivec.vcmpequd" => "__builtin_altivec_vcmpequd", + "llvm.ppc.altivec.vcmpequd.p" => "__builtin_altivec_vcmpequd_p", "llvm.ppc.altivec.vcmpequh" => "__builtin_altivec_vcmpequh", "llvm.ppc.altivec.vcmpequh.p" => "__builtin_altivec_vcmpequh_p", + "llvm.ppc.altivec.vcmpequq" => "__builtin_altivec_vcmpequq", + "llvm.ppc.altivec.vcmpequq.p" => "__builtin_altivec_vcmpequq_p", "llvm.ppc.altivec.vcmpequw" => "__builtin_altivec_vcmpequw", "llvm.ppc.altivec.vcmpequw.p" => "__builtin_altivec_vcmpequw_p", "llvm.ppc.altivec.vcmpgefp" => "__builtin_altivec_vcmpgefp", @@ -2074,19 +2365,85 @@ match name { "llvm.ppc.altivec.vcmpgtfp.p" => "__builtin_altivec_vcmpgtfp_p", "llvm.ppc.altivec.vcmpgtsb" => "__builtin_altivec_vcmpgtsb", "llvm.ppc.altivec.vcmpgtsb.p" => "__builtin_altivec_vcmpgtsb_p", + "llvm.ppc.altivec.vcmpgtsd" => "__builtin_altivec_vcmpgtsd", + "llvm.ppc.altivec.vcmpgtsd.p" => "__builtin_altivec_vcmpgtsd_p", "llvm.ppc.altivec.vcmpgtsh" => "__builtin_altivec_vcmpgtsh", "llvm.ppc.altivec.vcmpgtsh.p" => "__builtin_altivec_vcmpgtsh_p", + "llvm.ppc.altivec.vcmpgtsq" => "__builtin_altivec_vcmpgtsq", + "llvm.ppc.altivec.vcmpgtsq.p" => "__builtin_altivec_vcmpgtsq_p", "llvm.ppc.altivec.vcmpgtsw" => "__builtin_altivec_vcmpgtsw", "llvm.ppc.altivec.vcmpgtsw.p" => "__builtin_altivec_vcmpgtsw_p", "llvm.ppc.altivec.vcmpgtub" => "__builtin_altivec_vcmpgtub", "llvm.ppc.altivec.vcmpgtub.p" => "__builtin_altivec_vcmpgtub_p", + "llvm.ppc.altivec.vcmpgtud" => "__builtin_altivec_vcmpgtud", + "llvm.ppc.altivec.vcmpgtud.p" => "__builtin_altivec_vcmpgtud_p", "llvm.ppc.altivec.vcmpgtuh" => "__builtin_altivec_vcmpgtuh", "llvm.ppc.altivec.vcmpgtuh.p" => "__builtin_altivec_vcmpgtuh_p", + "llvm.ppc.altivec.vcmpgtuq" => "__builtin_altivec_vcmpgtuq", + "llvm.ppc.altivec.vcmpgtuq.p" => "__builtin_altivec_vcmpgtuq_p", "llvm.ppc.altivec.vcmpgtuw" => "__builtin_altivec_vcmpgtuw", "llvm.ppc.altivec.vcmpgtuw.p" => "__builtin_altivec_vcmpgtuw_p", + "llvm.ppc.altivec.vcmpneb" => "__builtin_altivec_vcmpneb", + "llvm.ppc.altivec.vcmpneb.p" => "__builtin_altivec_vcmpneb_p", + "llvm.ppc.altivec.vcmpneh" => "__builtin_altivec_vcmpneh", + "llvm.ppc.altivec.vcmpneh.p" => "__builtin_altivec_vcmpneh_p", + "llvm.ppc.altivec.vcmpnew" => "__builtin_altivec_vcmpnew", + "llvm.ppc.altivec.vcmpnew.p" => "__builtin_altivec_vcmpnew_p", + "llvm.ppc.altivec.vcmpnezb" => "__builtin_altivec_vcmpnezb", + "llvm.ppc.altivec.vcmpnezb.p" => "__builtin_altivec_vcmpnezb_p", + "llvm.ppc.altivec.vcmpnezh" => "__builtin_altivec_vcmpnezh", + "llvm.ppc.altivec.vcmpnezh.p" => "__builtin_altivec_vcmpnezh_p", + "llvm.ppc.altivec.vcmpnezw" => "__builtin_altivec_vcmpnezw", + "llvm.ppc.altivec.vcmpnezw.p" => "__builtin_altivec_vcmpnezw_p", + "llvm.ppc.altivec.vcntmbb" => "__builtin_altivec_vcntmbb", + "llvm.ppc.altivec.vcntmbd" => "__builtin_altivec_vcntmbd", + "llvm.ppc.altivec.vcntmbh" => "__builtin_altivec_vcntmbh", + "llvm.ppc.altivec.vcntmbw" => "__builtin_altivec_vcntmbw", "llvm.ppc.altivec.vctsxs" => "__builtin_altivec_vctsxs", "llvm.ppc.altivec.vctuxs" => "__builtin_altivec_vctuxs", + "llvm.ppc.altivec.vctzdm" => "__builtin_altivec_vctzdm", + "llvm.ppc.altivec.vctzlsbb" => "__builtin_altivec_vctzlsbb", + "llvm.ppc.altivec.vexpandbm" => "__builtin_altivec_vexpandbm", + "llvm.ppc.altivec.vexpanddm" => "__builtin_altivec_vexpanddm", + "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", + "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm", + "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm", "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", + "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx", + "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx", + "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", + "llvm.ppc.altivec.vextdubvrx" => "__builtin_altivec_vextdubvrx", + "llvm.ppc.altivec.vextduhvlx" => "__builtin_altivec_vextduhvlx", + "llvm.ppc.altivec.vextduhvrx" => "__builtin_altivec_vextduhvrx", + "llvm.ppc.altivec.vextduwvlx" => "__builtin_altivec_vextduwvlx", + "llvm.ppc.altivec.vextduwvrx" => "__builtin_altivec_vextduwvrx", + "llvm.ppc.altivec.vextractbm" => "__builtin_altivec_vextractbm", + "llvm.ppc.altivec.vextractdm" => "__builtin_altivec_vextractdm", + "llvm.ppc.altivec.vextracthm" => "__builtin_altivec_vextracthm", + "llvm.ppc.altivec.vextractqm" => "__builtin_altivec_vextractqm", + "llvm.ppc.altivec.vextractwm" => "__builtin_altivec_vextractwm", + "llvm.ppc.altivec.vextsb2d" => "__builtin_altivec_vextsb2d", + "llvm.ppc.altivec.vextsb2w" => "__builtin_altivec_vextsb2w", + "llvm.ppc.altivec.vextsd2q" => "__builtin_altivec_vextsd2q", + "llvm.ppc.altivec.vextsh2d" => "__builtin_altivec_vextsh2d", + "llvm.ppc.altivec.vextsh2w" => "__builtin_altivec_vextsh2w", + "llvm.ppc.altivec.vextsw2d" => "__builtin_altivec_vextsw2d", + "llvm.ppc.altivec.vgbbd" => "__builtin_altivec_vgbbd", + "llvm.ppc.altivec.vgnb" => "__builtin_altivec_vgnb", + "llvm.ppc.altivec.vinsblx" => "__builtin_altivec_vinsblx", + "llvm.ppc.altivec.vinsbrx" => "__builtin_altivec_vinsbrx", + "llvm.ppc.altivec.vinsbvlx" => "__builtin_altivec_vinsbvlx", + "llvm.ppc.altivec.vinsbvrx" => "__builtin_altivec_vinsbvrx", + "llvm.ppc.altivec.vinsdlx" => "__builtin_altivec_vinsdlx", + "llvm.ppc.altivec.vinsdrx" => "__builtin_altivec_vinsdrx", + "llvm.ppc.altivec.vinshlx" => "__builtin_altivec_vinshlx", + "llvm.ppc.altivec.vinshrx" => "__builtin_altivec_vinshrx", + "llvm.ppc.altivec.vinshvlx" => "__builtin_altivec_vinshvlx", + "llvm.ppc.altivec.vinshvrx" => "__builtin_altivec_vinshvrx", + "llvm.ppc.altivec.vinswlx" => "__builtin_altivec_vinswlx", + "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx", + "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx", + "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx", "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", @@ -2106,29 +2463,43 @@ match name { "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", + "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud", "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", "llvm.ppc.altivec.vmsumshm" => "__builtin_altivec_vmsumshm", "llvm.ppc.altivec.vmsumshs" => "__builtin_altivec_vmsumshs", "llvm.ppc.altivec.vmsumubm" => "__builtin_altivec_vmsumubm", + "llvm.ppc.altivec.vmsumudm" => "__builtin_altivec_vmsumudm", "llvm.ppc.altivec.vmsumuhm" => "__builtin_altivec_vmsumuhm", "llvm.ppc.altivec.vmsumuhs" => "__builtin_altivec_vmsumuhs", "llvm.ppc.altivec.vmulesb" => "__builtin_altivec_vmulesb", "llvm.ppc.altivec.vmulesh" => "__builtin_altivec_vmulesh", + "llvm.ppc.altivec.vmulesw" => "__builtin_altivec_vmulesw", "llvm.ppc.altivec.vmuleub" => "__builtin_altivec_vmuleub", "llvm.ppc.altivec.vmuleuh" => "__builtin_altivec_vmuleuh", + "llvm.ppc.altivec.vmuleuw" => "__builtin_altivec_vmuleuw", "llvm.ppc.altivec.vmulosb" => "__builtin_altivec_vmulosb", "llvm.ppc.altivec.vmulosh" => "__builtin_altivec_vmulosh", + "llvm.ppc.altivec.vmulosw" => "__builtin_altivec_vmulosw", "llvm.ppc.altivec.vmuloub" => "__builtin_altivec_vmuloub", "llvm.ppc.altivec.vmulouh" => "__builtin_altivec_vmulouh", + "llvm.ppc.altivec.vmulouw" => "__builtin_altivec_vmulouw", "llvm.ppc.altivec.vnmsubfp" => "__builtin_altivec_vnmsubfp", + "llvm.ppc.altivec.vpdepd" => "__builtin_altivec_vpdepd", "llvm.ppc.altivec.vperm" => "__builtin_altivec_vperm_4si", + "llvm.ppc.altivec.vpextd" => "__builtin_altivec_vpextd", "llvm.ppc.altivec.vpkpx" => "__builtin_altivec_vpkpx", + "llvm.ppc.altivec.vpksdss" => "__builtin_altivec_vpksdss", + "llvm.ppc.altivec.vpksdus" => "__builtin_altivec_vpksdus", "llvm.ppc.altivec.vpkshss" => "__builtin_altivec_vpkshss", "llvm.ppc.altivec.vpkshus" => "__builtin_altivec_vpkshus", "llvm.ppc.altivec.vpkswss" => "__builtin_altivec_vpkswss", "llvm.ppc.altivec.vpkswus" => "__builtin_altivec_vpkswus", + "llvm.ppc.altivec.vpkudus" => "__builtin_altivec_vpkudus", "llvm.ppc.altivec.vpkuhus" => "__builtin_altivec_vpkuhus", "llvm.ppc.altivec.vpkuwus" => "__builtin_altivec_vpkuwus", + "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd", + "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq", + "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw", "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", @@ -2141,6 +2512,7 @@ match name { "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", + "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", @@ -2149,10 +2521,21 @@ match name { "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", + "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", + "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", + "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", + "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr", + "llvm.ppc.altivec.vstribr.p" => "__builtin_altivec_vstribr_p", + "llvm.ppc.altivec.vstrihl" => "__builtin_altivec_vstrihl", + "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", + "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", + "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", + "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", + "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", @@ -2167,9 +2550,150 @@ match name { "llvm.ppc.altivec.vupkhpx" => "__builtin_altivec_vupkhpx", "llvm.ppc.altivec.vupkhsb" => "__builtin_altivec_vupkhsb", "llvm.ppc.altivec.vupkhsh" => "__builtin_altivec_vupkhsh", + "llvm.ppc.altivec.vupkhsw" => "__builtin_altivec_vupkhsw", "llvm.ppc.altivec.vupklpx" => "__builtin_altivec_vupklpx", "llvm.ppc.altivec.vupklsb" => "__builtin_altivec_vupklsb", "llvm.ppc.altivec.vupklsh" => "__builtin_altivec_vupklsh", + "llvm.ppc.altivec.vupklsw" => "__builtin_altivec_vupklsw", + "llvm.ppc.bcdadd" => "__builtin_ppc_bcdadd", + "llvm.ppc.bcdadd.p" => "__builtin_ppc_bcdadd_p", + "llvm.ppc.bcdsub" => "__builtin_ppc_bcdsub", + "llvm.ppc.bcdsub.p" => "__builtin_ppc_bcdsub_p", + "llvm.ppc.bpermd" => "__builtin_bpermd", + "llvm.ppc.cfuged" => "__builtin_cfuged", + "llvm.ppc.cmpeqb" => "__builtin_ppc_cmpeqb", + "llvm.ppc.cmprb" => "__builtin_ppc_cmprb", + "llvm.ppc.cntlzdm" => "__builtin_cntlzdm", + "llvm.ppc.cnttzdm" => "__builtin_cnttzdm", + "llvm.ppc.compare.exp.eq" => "__builtin_ppc_compare_exp_eq", + "llvm.ppc.compare.exp.gt" => "__builtin_ppc_compare_exp_gt", + "llvm.ppc.compare.exp.lt" => "__builtin_ppc_compare_exp_lt", + "llvm.ppc.compare.exp.uo" => "__builtin_ppc_compare_exp_uo", + "llvm.ppc.darn" => "__builtin_darn", + "llvm.ppc.darn32" => "__builtin_darn_32", + "llvm.ppc.darnraw" => "__builtin_darn_raw", + "llvm.ppc.dcbf" => "__builtin_dcbf", + "llvm.ppc.dcbfl" => "__builtin_ppc_dcbfl", + "llvm.ppc.dcbflp" => "__builtin_ppc_dcbflp", + "llvm.ppc.dcbst" => "__builtin_ppc_dcbst", + "llvm.ppc.dcbt" => "__builtin_ppc_dcbt", + "llvm.ppc.dcbtst" => "__builtin_ppc_dcbtst", + "llvm.ppc.dcbtstt" => "__builtin_ppc_dcbtstt", + "llvm.ppc.dcbtt" => "__builtin_ppc_dcbtt", + "llvm.ppc.dcbz" => "__builtin_ppc_dcbz", + "llvm.ppc.divde" => "__builtin_divde", + "llvm.ppc.divdeu" => "__builtin_divdeu", + "llvm.ppc.divf128.round.to.odd" => "__builtin_divf128_round_to_odd", + "llvm.ppc.divwe" => "__builtin_divwe", + "llvm.ppc.divweu" => "__builtin_divweu", + "llvm.ppc.eieio" => "__builtin_ppc_eieio", + "llvm.ppc.extract.exp" => "__builtin_ppc_extract_exp", + "llvm.ppc.extract.sig" => "__builtin_ppc_extract_sig", + "llvm.ppc.fcfid" => "__builtin_ppc_fcfid", + "llvm.ppc.fcfud" => "__builtin_ppc_fcfud", + "llvm.ppc.fctid" => "__builtin_ppc_fctid", + "llvm.ppc.fctidz" => "__builtin_ppc_fctidz", + "llvm.ppc.fctiw" => "__builtin_ppc_fctiw", + "llvm.ppc.fctiwz" => "__builtin_ppc_fctiwz", + "llvm.ppc.fctudz" => "__builtin_ppc_fctudz", + "llvm.ppc.fctuwz" => "__builtin_ppc_fctuwz", + "llvm.ppc.fmaf128.round.to.odd" => "__builtin_fmaf128_round_to_odd", + "llvm.ppc.fmsub" => "__builtin_ppc_fmsub", + "llvm.ppc.fmsubs" => "__builtin_ppc_fmsubs", + "llvm.ppc.fnmadd" => "__builtin_ppc_fnmadd", + "llvm.ppc.fnmadds" => "__builtin_ppc_fnmadds", + "llvm.ppc.fre" => "__builtin_ppc_fre", + "llvm.ppc.fres" => "__builtin_ppc_fres", + "llvm.ppc.frsqrte" => "__builtin_ppc_frsqrte", + "llvm.ppc.frsqrtes" => "__builtin_ppc_frsqrtes", + "llvm.ppc.fsel" => "__builtin_ppc_fsel", + "llvm.ppc.fsels" => "__builtin_ppc_fsels", + "llvm.ppc.get.texasr" => "__builtin_get_texasr", + "llvm.ppc.get.texasru" => "__builtin_get_texasru", + "llvm.ppc.get.tfhar" => "__builtin_get_tfhar", + "llvm.ppc.get.tfiar" => "__builtin_get_tfiar", + "llvm.ppc.icbt" => "__builtin_ppc_icbt", + "llvm.ppc.insert.exp" => "__builtin_ppc_insert_exp", + "llvm.ppc.iospace.eieio" => "__builtin_ppc_iospace_eieio", + "llvm.ppc.iospace.lwsync" => "__builtin_ppc_iospace_lwsync", + "llvm.ppc.iospace.sync" => "__builtin_ppc_iospace_sync", + "llvm.ppc.isync" => "__builtin_ppc_isync", + "llvm.ppc.load4r" => "__builtin_ppc_load4r", + "llvm.ppc.load8r" => "__builtin_ppc_load8r", + "llvm.ppc.lwsync" => "__builtin_ppc_lwsync", + "llvm.ppc.maddhd" => "__builtin_ppc_maddhd", + "llvm.ppc.maddhdu" => "__builtin_ppc_maddhdu", + "llvm.ppc.maddld" => "__builtin_ppc_maddld", + "llvm.ppc.mfmsr" => "__builtin_ppc_mfmsr", + "llvm.ppc.mftbu" => "__builtin_ppc_mftbu", + "llvm.ppc.mtfsb0" => "__builtin_ppc_mtfsb0", + "llvm.ppc.mtfsb1" => "__builtin_ppc_mtfsb1", + "llvm.ppc.mtfsfi" => "__builtin_ppc_mtfsfi", + "llvm.ppc.mtmsr" => "__builtin_ppc_mtmsr", + "llvm.ppc.mulf128.round.to.odd" => "__builtin_mulf128_round_to_odd", + "llvm.ppc.mulhd" => "__builtin_ppc_mulhd", + "llvm.ppc.mulhdu" => "__builtin_ppc_mulhdu", + "llvm.ppc.mulhw" => "__builtin_ppc_mulhw", + "llvm.ppc.mulhwu" => "__builtin_ppc_mulhwu", + "llvm.ppc.pack.longdouble" => "__builtin_pack_longdouble", + "llvm.ppc.pdepd" => "__builtin_pdepd", + "llvm.ppc.pextd" => "__builtin_pextd", + "llvm.ppc.readflm" => "__builtin_readflm", + "llvm.ppc.scalar.extract.expq" => "__builtin_vsx_scalar_extract_expq", + "llvm.ppc.scalar.insert.exp.qp" => "__builtin_vsx_scalar_insert_exp_qp", + "llvm.ppc.set.texasr" => "__builtin_set_texasr", + "llvm.ppc.set.texasru" => "__builtin_set_texasru", + "llvm.ppc.set.tfhar" => "__builtin_set_tfhar", + "llvm.ppc.set.tfiar" => "__builtin_set_tfiar", + "llvm.ppc.setb" => "__builtin_ppc_setb", + "llvm.ppc.setflm" => "__builtin_setflm", + "llvm.ppc.setrnd" => "__builtin_setrnd", + "llvm.ppc.sqrtf128.round.to.odd" => "__builtin_sqrtf128_round_to_odd", + "llvm.ppc.stbcx" => "__builtin_ppc_stbcx", + "llvm.ppc.stdcx" => "__builtin_ppc_stdcx", + "llvm.ppc.stfiw" => "__builtin_ppc_stfiw", + "llvm.ppc.store2r" => "__builtin_ppc_store2r", + "llvm.ppc.store4r" => "__builtin_ppc_store4r", + "llvm.ppc.store8r" => "__builtin_ppc_store8r", + "llvm.ppc.stwcx" => "__builtin_ppc_stwcx", + "llvm.ppc.subf128.round.to.odd" => "__builtin_subf128_round_to_odd", + "llvm.ppc.sync" => "__builtin_ppc_sync", + "llvm.ppc.tabort" => "__builtin_tabort", + "llvm.ppc.tabortdc" => "__builtin_tabortdc", + "llvm.ppc.tabortdci" => "__builtin_tabortdci", + "llvm.ppc.tabortwc" => "__builtin_tabortwc", + "llvm.ppc.tabortwci" => "__builtin_tabortwci", + "llvm.ppc.tbegin" => "__builtin_tbegin", + "llvm.ppc.tcheck" => "__builtin_tcheck", + "llvm.ppc.tdw" => "__builtin_ppc_tdw", + "llvm.ppc.tend" => "__builtin_tend", + "llvm.ppc.tendall" => "__builtin_tendall", + "llvm.ppc.trap" => "__builtin_ppc_trap", + "llvm.ppc.trapd" => "__builtin_ppc_trapd", + "llvm.ppc.trechkpt" => "__builtin_trechkpt", + "llvm.ppc.treclaim" => "__builtin_treclaim", + "llvm.ppc.tresume" => "__builtin_tresume", + "llvm.ppc.truncf128.round.to.odd" => "__builtin_truncf128_round_to_odd", + "llvm.ppc.tsr" => "__builtin_tsr", + "llvm.ppc.tsuspend" => "__builtin_tsuspend", + "llvm.ppc.ttest" => "__builtin_ttest", + "llvm.ppc.tw" => "__builtin_ppc_tw", + "llvm.ppc.unpack.longdouble" => "__builtin_unpack_longdouble", + "llvm.ppc.vsx.xvcmpeqdp.p" => "__builtin_vsx_xvcmpeqdp_p", + "llvm.ppc.vsx.xvcmpeqsp.p" => "__builtin_vsx_xvcmpeqsp_p", + "llvm.ppc.vsx.xvcmpgedp.p" => "__builtin_vsx_xvcmpgedp_p", + "llvm.ppc.vsx.xvcmpgesp.p" => "__builtin_vsx_xvcmpgesp_p", + "llvm.ppc.vsx.xvcmpgtdp.p" => "__builtin_vsx_xvcmpgtdp_p", + "llvm.ppc.vsx.xvcmpgtsp.p" => "__builtin_vsx_xvcmpgtsp_p", + "llvm.ppc.vsx.xvredp" => "__builtin_vsx_xvredp", + "llvm.ppc.vsx.xvresp" => "__builtin_vsx_xvresp", + "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", + "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", + "llvm.ppc.vsx.xxblendvb" => "__builtin_vsx_xxblendvb", + "llvm.ppc.vsx.xxblendvd" => "__builtin_vsx_xxblendvd", + "llvm.ppc.vsx.xxblendvh" => "__builtin_vsx_xxblendvh", + "llvm.ppc.vsx.xxblendvw" => "__builtin_vsx_xxblendvw", + "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", // ptx "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", @@ -2189,15 +2713,76 @@ match name { "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", + // s390 + "llvm.s390.efpc" => "__builtin_s390_efpc", + "llvm.s390.etnd" => "__builtin_tx_nesting_depth", + "llvm.s390.lcbb" => "__builtin_s390_lcbb", + "llvm.s390.ppa.txassist" => "__builtin_tx_assist", + "llvm.s390.sfpc" => "__builtin_s390_sfpc", + "llvm.s390.tend" => "__builtin_tend", + "llvm.s390.vcfn" => "__builtin_s390_vcfn", + "llvm.s390.vclfnhs" => "__builtin_s390_vclfnhs", + "llvm.s390.vclfnls" => "__builtin_s390_vclfnls", + "llvm.s390.vcnf" => "__builtin_s390_vcnf", + "llvm.s390.vcrnfs" => "__builtin_s390_vcrnfs", + "llvm.s390.vlbb" => "__builtin_s390_vlbb", + "llvm.s390.vll" => "__builtin_s390_vll", + "llvm.s390.vlrl" => "__builtin_s390_vlrl", + "llvm.s390.vmslg" => "__builtin_s390_vmslg", + "llvm.s390.vpdi" => "__builtin_s390_vpdi", + "llvm.s390.vperm" => "__builtin_s390_vperm", + "llvm.s390.vsld" => "__builtin_s390_vsld", + "llvm.s390.vsldb" => "__builtin_s390_vsldb", + "llvm.s390.vsrd" => "__builtin_s390_vsrd", + "llvm.s390.vstl" => "__builtin_s390_vstl", + "llvm.s390.vstrl" => "__builtin_s390_vstrl", + // ve + "llvm.ve.vl.extract.vm512l" => "__builtin_ve_vl_extract_vm512l", + "llvm.ve.vl.extract.vm512u" => "__builtin_ve_vl_extract_vm512u", + "llvm.ve.vl.insert.vm512l" => "__builtin_ve_vl_insert_vm512l", + "llvm.ve.vl.insert.vm512u" => "__builtin_ve_vl_insert_vm512u", + "llvm.ve.vl.pack.f32a" => "__builtin_ve_vl_pack_f32a", + "llvm.ve.vl.pack.f32p" => "__builtin_ve_vl_pack_f32p", // x86 + "llvm.x86.3dnow.pavgusb" => "__builtin_ia32_pavgusb", + "llvm.x86.3dnow.pf2id" => "__builtin_ia32_pf2id", + "llvm.x86.3dnow.pfacc" => "__builtin_ia32_pfacc", + "llvm.x86.3dnow.pfadd" => "__builtin_ia32_pfadd", + "llvm.x86.3dnow.pfcmpeq" => "__builtin_ia32_pfcmpeq", + "llvm.x86.3dnow.pfcmpge" => "__builtin_ia32_pfcmpge", + "llvm.x86.3dnow.pfcmpgt" => "__builtin_ia32_pfcmpgt", + "llvm.x86.3dnow.pfmax" => "__builtin_ia32_pfmax", + "llvm.x86.3dnow.pfmin" => "__builtin_ia32_pfmin", + "llvm.x86.3dnow.pfmul" => "__builtin_ia32_pfmul", + "llvm.x86.3dnow.pfrcp" => "__builtin_ia32_pfrcp", + "llvm.x86.3dnow.pfrcpit1" => "__builtin_ia32_pfrcpit1", + "llvm.x86.3dnow.pfrcpit2" => "__builtin_ia32_pfrcpit2", + "llvm.x86.3dnow.pfrsqit1" => "__builtin_ia32_pfrsqit1", + "llvm.x86.3dnow.pfrsqrt" => "__builtin_ia32_pfrsqrt", + "llvm.x86.3dnow.pfsub" => "__builtin_ia32_pfsub", + "llvm.x86.3dnow.pfsubr" => "__builtin_ia32_pfsubr", + "llvm.x86.3dnow.pi2fd" => "__builtin_ia32_pi2fd", + "llvm.x86.3dnow.pmulhrw" => "__builtin_ia32_pmulhrw", + "llvm.x86.3dnowa.pf2iw" => "__builtin_ia32_pf2iw", + "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc", + "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc", + "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw", "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", + "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", + "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", "llvm.x86.aesni.aesdeclast" => "__builtin_ia32_aesdeclast128", + "llvm.x86.aesni.aesdeclast.256" => "__builtin_ia32_aesdeclast256", + "llvm.x86.aesni.aesdeclast.512" => "__builtin_ia32_aesdeclast512", "llvm.x86.aesni.aesenc" => "__builtin_ia32_aesenc128", + "llvm.x86.aesni.aesenc.256" => "__builtin_ia32_aesenc256", + "llvm.x86.aesni.aesenc.512" => "__builtin_ia32_aesenc512", "llvm.x86.aesni.aesenclast" => "__builtin_ia32_aesenclast128", + "llvm.x86.aesni.aesenclast.256" => "__builtin_ia32_aesenclast256", + "llvm.x86.aesni.aesenclast.512" => "__builtin_ia32_aesenclast512", "llvm.x86.aesni.aesimc" => "__builtin_ia32_aesimc128", "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", @@ -2413,18 +2998,53 @@ match name { "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", + "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", + "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", + "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", + "llvm.x86.avx512.broadcastmb.256" => "__builtin_ia32_broadcastmb256", + "llvm.x86.avx512.broadcastmb.512" => "__builtin_ia32_broadcastmb512", + "llvm.x86.avx512.broadcastmw.128" => "__builtin_ia32_broadcastmw128", + "llvm.x86.avx512.broadcastmw.256" => "__builtin_ia32_broadcastmw256", + "llvm.x86.avx512.broadcastmw.512" => "__builtin_ia32_broadcastmw512", + "llvm.x86.avx512.conflict.d.128" => "__builtin_ia32_vpconflictsi_128", + "llvm.x86.avx512.conflict.d.256" => "__builtin_ia32_vpconflictsi_256", + "llvm.x86.avx512.conflict.d.512" => "__builtin_ia32_vpconflictsi_512", + "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", + "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", + "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", + "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", + "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", + "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", + "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", + "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", + "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", + "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", - "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", - "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", + "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", + "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", + "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", + "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", + "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", + "llvm.x86.avx512.div.pd.512" => "__builtin_ia32_divpd512", + "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", + "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", + "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", @@ -2446,27 +3066,101 @@ match name { "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", + "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", + "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", + "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", + "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", + "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", + "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", "llvm.x86.avx512.mask.cvtpd2ps.512" => "__builtin_ia32_cvtpd2ps512_mask", + "llvm.x86.avx512.mask.cvtpd2qq.128" => "__builtin_ia32_cvtpd2qq128_mask", + "llvm.x86.avx512.mask.cvtpd2qq.256" => "__builtin_ia32_cvtpd2qq256_mask", + "llvm.x86.avx512.mask.cvtpd2qq.512" => "__builtin_ia32_cvtpd2qq512_mask", + "llvm.x86.avx512.mask.cvtpd2udq.128" => "__builtin_ia32_cvtpd2udq128_mask", + "llvm.x86.avx512.mask.cvtpd2udq.256" => "__builtin_ia32_cvtpd2udq256_mask", "llvm.x86.avx512.mask.cvtpd2udq.512" => "__builtin_ia32_cvtpd2udq512_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.128" => "__builtin_ia32_cvtpd2uqq128_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.256" => "__builtin_ia32_cvtpd2uqq256_mask", + "llvm.x86.avx512.mask.cvtpd2uqq.512" => "__builtin_ia32_cvtpd2uqq512_mask", + "llvm.x86.avx512.mask.cvtps2dq.128" => "__builtin_ia32_cvtps2dq128_mask", + "llvm.x86.avx512.mask.cvtps2dq.256" => "__builtin_ia32_cvtps2dq256_mask", "llvm.x86.avx512.mask.cvtps2dq.512" => "__builtin_ia32_cvtps2dq512_mask", + "llvm.x86.avx512.mask.cvtps2pd.512" => "__builtin_ia32_cvtps2pd512_mask", + "llvm.x86.avx512.mask.cvtps2qq.128" => "__builtin_ia32_cvtps2qq128_mask", + "llvm.x86.avx512.mask.cvtps2qq.256" => "__builtin_ia32_cvtps2qq256_mask", + "llvm.x86.avx512.mask.cvtps2qq.512" => "__builtin_ia32_cvtps2qq512_mask", + "llvm.x86.avx512.mask.cvtps2udq.128" => "__builtin_ia32_cvtps2udq128_mask", + "llvm.x86.avx512.mask.cvtps2udq.256" => "__builtin_ia32_cvtps2udq256_mask", "llvm.x86.avx512.mask.cvtps2udq.512" => "__builtin_ia32_cvtps2udq512_mask", + "llvm.x86.avx512.mask.cvtps2uqq.128" => "__builtin_ia32_cvtps2uqq128_mask", + "llvm.x86.avx512.mask.cvtps2uqq.256" => "__builtin_ia32_cvtps2uqq256_mask", + "llvm.x86.avx512.mask.cvtps2uqq.512" => "__builtin_ia32_cvtps2uqq512_mask", + "llvm.x86.avx512.mask.cvtqq2ps.128" => "__builtin_ia32_cvtqq2ps128_mask", + "llvm.x86.avx512.mask.cvtsd2ss.round" => "__builtin_ia32_cvtsd2ss_round_mask", + "llvm.x86.avx512.mask.cvtss2sd.round" => "__builtin_ia32_cvtss2sd_round_mask", + "llvm.x86.avx512.mask.cvttpd2dq.128" => "__builtin_ia32_cvttpd2dq128_mask", "llvm.x86.avx512.mask.cvttpd2dq.512" => "__builtin_ia32_cvttpd2dq512_mask", + "llvm.x86.avx512.mask.cvttpd2qq.128" => "__builtin_ia32_cvttpd2qq128_mask", + "llvm.x86.avx512.mask.cvttpd2qq.256" => "__builtin_ia32_cvttpd2qq256_mask", + "llvm.x86.avx512.mask.cvttpd2qq.512" => "__builtin_ia32_cvttpd2qq512_mask", + "llvm.x86.avx512.mask.cvttpd2udq.128" => "__builtin_ia32_cvttpd2udq128_mask", + "llvm.x86.avx512.mask.cvttpd2udq.256" => "__builtin_ia32_cvttpd2udq256_mask", "llvm.x86.avx512.mask.cvttpd2udq.512" => "__builtin_ia32_cvttpd2udq512_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.128" => "__builtin_ia32_cvttpd2uqq128_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.256" => "__builtin_ia32_cvttpd2uqq256_mask", + "llvm.x86.avx512.mask.cvttpd2uqq.512" => "__builtin_ia32_cvttpd2uqq512_mask", "llvm.x86.avx512.mask.cvttps2dq.512" => "__builtin_ia32_cvttps2dq512_mask", + "llvm.x86.avx512.mask.cvttps2qq.128" => "__builtin_ia32_cvttps2qq128_mask", + "llvm.x86.avx512.mask.cvttps2qq.256" => "__builtin_ia32_cvttps2qq256_mask", + "llvm.x86.avx512.mask.cvttps2qq.512" => "__builtin_ia32_cvttps2qq512_mask", + "llvm.x86.avx512.mask.cvttps2udq.128" => "__builtin_ia32_cvttps2udq128_mask", + "llvm.x86.avx512.mask.cvttps2udq.256" => "__builtin_ia32_cvttps2udq256_mask", "llvm.x86.avx512.mask.cvttps2udq.512" => "__builtin_ia32_cvttps2udq512_mask", + "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", + "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", + "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", + "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", + "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", + "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", + "llvm.x86.avx512.mask.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_mask", + "llvm.x86.avx512.mask.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_mask", + "llvm.x86.avx512.mask.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_mask", + "llvm.x86.avx512.mask.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_mask", + "llvm.x86.avx512.mask.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_mask", + "llvm.x86.avx512.mask.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_mask", + "llvm.x86.avx512.mask.fixupimm.sd" => "__builtin_ia32_fixupimmsd_mask", + "llvm.x86.avx512.mask.fixupimm.ss" => "__builtin_ia32_fixupimmss_mask", + "llvm.x86.avx512.mask.fpclass.sd" => "__builtin_ia32_fpclasssd_mask", + "llvm.x86.avx512.mask.fpclass.ss" => "__builtin_ia32_fpclassss_mask", + "llvm.x86.avx512.mask.getexp.pd.128" => "__builtin_ia32_getexppd128_mask", + "llvm.x86.avx512.mask.getexp.pd.256" => "__builtin_ia32_getexppd256_mask", + "llvm.x86.avx512.mask.getexp.pd.512" => "__builtin_ia32_getexppd512_mask", + "llvm.x86.avx512.mask.getexp.ps.128" => "__builtin_ia32_getexpps128_mask", + "llvm.x86.avx512.mask.getexp.ps.256" => "__builtin_ia32_getexpps256_mask", + "llvm.x86.avx512.mask.getexp.ps.512" => "__builtin_ia32_getexpps512_mask", + "llvm.x86.avx512.mask.getexp.sd" => "__builtin_ia32_getexpsd128_round_mask", + "llvm.x86.avx512.mask.getexp.ss" => "__builtin_ia32_getexpss128_round_mask", + "llvm.x86.avx512.mask.getmant.pd.128" => "__builtin_ia32_getmantpd128_mask", + "llvm.x86.avx512.mask.getmant.pd.256" => "__builtin_ia32_getmantpd256_mask", + "llvm.x86.avx512.mask.getmant.pd.512" => "__builtin_ia32_getmantpd512_mask", + "llvm.x86.avx512.mask.getmant.ps.128" => "__builtin_ia32_getmantps128_mask", + "llvm.x86.avx512.mask.getmant.ps.256" => "__builtin_ia32_getmantps256_mask", + "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", + "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", + "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", @@ -2475,8 +3169,14 @@ match name { "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", + "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", + "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", + "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", + "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", + "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", + "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", @@ -2516,55 +3216,289 @@ match name { "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", + "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", + "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", + "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", + "llvm.x86.avx512.mask.pmov.db.mem.256" => "__builtin_ia32_pmovdb256mem_mask", + "llvm.x86.avx512.mask.pmov.db.mem.512" => "__builtin_ia32_pmovdb512mem_mask", + "llvm.x86.avx512.mask.pmov.dw.128" => "__builtin_ia32_pmovdw128_mask", + "llvm.x86.avx512.mask.pmov.dw.256" => "__builtin_ia32_pmovdw256_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.128" => "__builtin_ia32_pmovdw128mem_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.256" => "__builtin_ia32_pmovdw256mem_mask", + "llvm.x86.avx512.mask.pmov.dw.mem.512" => "__builtin_ia32_pmovdw512mem_mask", + "llvm.x86.avx512.mask.pmov.qb.128" => "__builtin_ia32_pmovqb128_mask", + "llvm.x86.avx512.mask.pmov.qb.256" => "__builtin_ia32_pmovqb256_mask", + "llvm.x86.avx512.mask.pmov.qb.512" => "__builtin_ia32_pmovqb512_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.128" => "__builtin_ia32_pmovqb128mem_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.256" => "__builtin_ia32_pmovqb256mem_mask", + "llvm.x86.avx512.mask.pmov.qb.mem.512" => "__builtin_ia32_pmovqb512mem_mask", + "llvm.x86.avx512.mask.pmov.qd.128" => "__builtin_ia32_pmovqd128_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.128" => "__builtin_ia32_pmovqd128mem_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.256" => "__builtin_ia32_pmovqd256mem_mask", + "llvm.x86.avx512.mask.pmov.qd.mem.512" => "__builtin_ia32_pmovqd512mem_mask", + "llvm.x86.avx512.mask.pmov.qw.128" => "__builtin_ia32_pmovqw128_mask", + "llvm.x86.avx512.mask.pmov.qw.256" => "__builtin_ia32_pmovqw256_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.128" => "__builtin_ia32_pmovqw128mem_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.256" => "__builtin_ia32_pmovqw256mem_mask", + "llvm.x86.avx512.mask.pmov.qw.mem.512" => "__builtin_ia32_pmovqw512mem_mask", + "llvm.x86.avx512.mask.pmov.wb.128" => "__builtin_ia32_pmovwb128_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.128" => "__builtin_ia32_pmovwb128mem_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.256" => "__builtin_ia32_pmovwb256mem_mask", + "llvm.x86.avx512.mask.pmov.wb.mem.512" => "__builtin_ia32_pmovwb512mem_mask", + "llvm.x86.avx512.mask.pmovs.db.128" => "__builtin_ia32_pmovsdb128_mask", + "llvm.x86.avx512.mask.pmovs.db.256" => "__builtin_ia32_pmovsdb256_mask", + "llvm.x86.avx512.mask.pmovs.db.512" => "__builtin_ia32_pmovsdb512_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.128" => "__builtin_ia32_pmovsdb128mem_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.256" => "__builtin_ia32_pmovsdb256mem_mask", + "llvm.x86.avx512.mask.pmovs.db.mem.512" => "__builtin_ia32_pmovsdb512mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.128" => "__builtin_ia32_pmovsdw128_mask", + "llvm.x86.avx512.mask.pmovs.dw.256" => "__builtin_ia32_pmovsdw256_mask", + "llvm.x86.avx512.mask.pmovs.dw.512" => "__builtin_ia32_pmovsdw512_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.128" => "__builtin_ia32_pmovsdw128mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.256" => "__builtin_ia32_pmovsdw256mem_mask", + "llvm.x86.avx512.mask.pmovs.dw.mem.512" => "__builtin_ia32_pmovsdw512mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.128" => "__builtin_ia32_pmovsqb128_mask", + "llvm.x86.avx512.mask.pmovs.qb.256" => "__builtin_ia32_pmovsqb256_mask", + "llvm.x86.avx512.mask.pmovs.qb.512" => "__builtin_ia32_pmovsqb512_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.128" => "__builtin_ia32_pmovsqb128mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.256" => "__builtin_ia32_pmovsqb256mem_mask", + "llvm.x86.avx512.mask.pmovs.qb.mem.512" => "__builtin_ia32_pmovsqb512mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.128" => "__builtin_ia32_pmovsqd128_mask", + "llvm.x86.avx512.mask.pmovs.qd.256" => "__builtin_ia32_pmovsqd256_mask", + "llvm.x86.avx512.mask.pmovs.qd.512" => "__builtin_ia32_pmovsqd512_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.128" => "__builtin_ia32_pmovsqd128mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.256" => "__builtin_ia32_pmovsqd256mem_mask", + "llvm.x86.avx512.mask.pmovs.qd.mem.512" => "__builtin_ia32_pmovsqd512mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.128" => "__builtin_ia32_pmovsqw128_mask", + "llvm.x86.avx512.mask.pmovs.qw.256" => "__builtin_ia32_pmovsqw256_mask", + "llvm.x86.avx512.mask.pmovs.qw.512" => "__builtin_ia32_pmovsqw512_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.128" => "__builtin_ia32_pmovsqw128mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.256" => "__builtin_ia32_pmovsqw256mem_mask", + "llvm.x86.avx512.mask.pmovs.qw.mem.512" => "__builtin_ia32_pmovsqw512mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.128" => "__builtin_ia32_pmovswb128_mask", + "llvm.x86.avx512.mask.pmovs.wb.256" => "__builtin_ia32_pmovswb256_mask", + "llvm.x86.avx512.mask.pmovs.wb.512" => "__builtin_ia32_pmovswb512_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.128" => "__builtin_ia32_pmovswb128mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.256" => "__builtin_ia32_pmovswb256mem_mask", + "llvm.x86.avx512.mask.pmovs.wb.mem.512" => "__builtin_ia32_pmovswb512mem_mask", + "llvm.x86.avx512.mask.pmovus.db.128" => "__builtin_ia32_pmovusdb128_mask", + "llvm.x86.avx512.mask.pmovus.db.256" => "__builtin_ia32_pmovusdb256_mask", + "llvm.x86.avx512.mask.pmovus.db.512" => "__builtin_ia32_pmovusdb512_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.128" => "__builtin_ia32_pmovusdb128mem_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.256" => "__builtin_ia32_pmovusdb256mem_mask", + "llvm.x86.avx512.mask.pmovus.db.mem.512" => "__builtin_ia32_pmovusdb512mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.128" => "__builtin_ia32_pmovusdw128_mask", + "llvm.x86.avx512.mask.pmovus.dw.256" => "__builtin_ia32_pmovusdw256_mask", + "llvm.x86.avx512.mask.pmovus.dw.512" => "__builtin_ia32_pmovusdw512_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.128" => "__builtin_ia32_pmovusdw128mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.256" => "__builtin_ia32_pmovusdw256mem_mask", + "llvm.x86.avx512.mask.pmovus.dw.mem.512" => "__builtin_ia32_pmovusdw512mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.128" => "__builtin_ia32_pmovusqb128_mask", + "llvm.x86.avx512.mask.pmovus.qb.256" => "__builtin_ia32_pmovusqb256_mask", + "llvm.x86.avx512.mask.pmovus.qb.512" => "__builtin_ia32_pmovusqb512_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.128" => "__builtin_ia32_pmovusqb128mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.256" => "__builtin_ia32_pmovusqb256mem_mask", + "llvm.x86.avx512.mask.pmovus.qb.mem.512" => "__builtin_ia32_pmovusqb512mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.128" => "__builtin_ia32_pmovusqd128_mask", + "llvm.x86.avx512.mask.pmovus.qd.256" => "__builtin_ia32_pmovusqd256_mask", + "llvm.x86.avx512.mask.pmovus.qd.512" => "__builtin_ia32_pmovusqd512_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.128" => "__builtin_ia32_pmovusqd128mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.256" => "__builtin_ia32_pmovusqd256mem_mask", + "llvm.x86.avx512.mask.pmovus.qd.mem.512" => "__builtin_ia32_pmovusqd512mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.128" => "__builtin_ia32_pmovusqw128_mask", + "llvm.x86.avx512.mask.pmovus.qw.256" => "__builtin_ia32_pmovusqw256_mask", + "llvm.x86.avx512.mask.pmovus.qw.512" => "__builtin_ia32_pmovusqw512_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.128" => "__builtin_ia32_pmovusqw128mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.256" => "__builtin_ia32_pmovusqw256mem_mask", + "llvm.x86.avx512.mask.pmovus.qw.mem.512" => "__builtin_ia32_pmovusqw512mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.128" => "__builtin_ia32_pmovuswb128_mask", + "llvm.x86.avx512.mask.pmovus.wb.256" => "__builtin_ia32_pmovuswb256_mask", + "llvm.x86.avx512.mask.pmovus.wb.512" => "__builtin_ia32_pmovuswb512_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", + "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", + "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", + "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", + "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", + "llvm.x86.avx512.mask.range.ps.128" => "__builtin_ia32_rangeps128_mask", + "llvm.x86.avx512.mask.range.ps.256" => "__builtin_ia32_rangeps256_mask", + "llvm.x86.avx512.mask.range.ps.512" => "__builtin_ia32_rangeps512_mask", + "llvm.x86.avx512.mask.range.sd" => "__builtin_ia32_rangesd128_round_mask", + "llvm.x86.avx512.mask.range.ss" => "__builtin_ia32_rangess128_round_mask", + "llvm.x86.avx512.mask.reduce.pd.128" => "__builtin_ia32_reducepd128_mask", + "llvm.x86.avx512.mask.reduce.pd.256" => "__builtin_ia32_reducepd256_mask", + "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask", + "llvm.x86.avx512.mask.reduce.ps.128" => "__builtin_ia32_reduceps128_mask", + "llvm.x86.avx512.mask.reduce.ps.256" => "__builtin_ia32_reduceps256_mask", + "llvm.x86.avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask", + "llvm.x86.avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask", + "llvm.x86.avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask", + "llvm.x86.avx512.mask.rndscale.pd.128" => "__builtin_ia32_rndscalepd_128_mask", + "llvm.x86.avx512.mask.rndscale.pd.256" => "__builtin_ia32_rndscalepd_256_mask", "llvm.x86.avx512.mask.rndscale.pd.512" => "__builtin_ia32_rndscalepd_mask", + "llvm.x86.avx512.mask.rndscale.ps.128" => "__builtin_ia32_rndscaleps_128_mask", + "llvm.x86.avx512.mask.rndscale.ps.256" => "__builtin_ia32_rndscaleps_256_mask", "llvm.x86.avx512.mask.rndscale.ps.512" => "__builtin_ia32_rndscaleps_mask", + "llvm.x86.avx512.mask.rndscale.sd" => "__builtin_ia32_rndscalesd_round_mask", + "llvm.x86.avx512.mask.rndscale.ss" => "__builtin_ia32_rndscaless_round_mask", + "llvm.x86.avx512.mask.scalef.pd.128" => "__builtin_ia32_scalefpd128_mask", + "llvm.x86.avx512.mask.scalef.pd.256" => "__builtin_ia32_scalefpd256_mask", + "llvm.x86.avx512.mask.scalef.pd.512" => "__builtin_ia32_scalefpd512_mask", + "llvm.x86.avx512.mask.scalef.ps.128" => "__builtin_ia32_scalefps128_mask", + "llvm.x86.avx512.mask.scalef.ps.256" => "__builtin_ia32_scalefps256_mask", + "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", + "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", + "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", + "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", + "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", + "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", + "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", + "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", + "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", + "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.128" => "__builtin_ia32_fixupimmps128_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.256" => "__builtin_ia32_fixupimmps256_maskz", + "llvm.x86.avx512.maskz.fixupimm.ps.512" => "__builtin_ia32_fixupimmps512_maskz", + "llvm.x86.avx512.maskz.fixupimm.sd" => "__builtin_ia32_fixupimmsd_maskz", + "llvm.x86.avx512.maskz.fixupimm.ss" => "__builtin_ia32_fixupimmss_maskz", + "llvm.x86.avx512.max.pd.512" => "__builtin_ia32_maxpd512", + "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", + "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", + "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", + "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", + "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", + "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", + "llvm.x86.avx512.packsswb.512" => "__builtin_ia32_packsswb512", + "llvm.x86.avx512.packusdw.512" => "__builtin_ia32_packusdw512", + "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", + "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", + "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", + "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", + "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", + "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", + "llvm.x86.avx512.permvar.di.512" => "__builtin_ia32_permvardi512", + "llvm.x86.avx512.permvar.hi.128" => "__builtin_ia32_permvarhi128", + "llvm.x86.avx512.permvar.hi.256" => "__builtin_ia32_permvarhi256", + "llvm.x86.avx512.permvar.hi.512" => "__builtin_ia32_permvarhi512", + "llvm.x86.avx512.permvar.qi.128" => "__builtin_ia32_permvarqi128", + "llvm.x86.avx512.permvar.qi.256" => "__builtin_ia32_permvarqi256", + "llvm.x86.avx512.permvar.qi.512" => "__builtin_ia32_permvarqi512", + "llvm.x86.avx512.permvar.sf.512" => "__builtin_ia32_permvarsf512", + "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", + "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", + "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", + "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", + "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", + "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", + "llvm.x86.avx512.pmultishift.qb.128" => "__builtin_ia32_vpmultishiftqb128", + "llvm.x86.avx512.pmultishift.qb.256" => "__builtin_ia32_vpmultishiftqb256", + "llvm.x86.avx512.pmultishift.qb.512" => "__builtin_ia32_vpmultishiftqb512", + "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", + "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", + "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", + "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", + "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", + "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", + "llvm.x86.avx512.pslli.q.512" => "__builtin_ia32_psllqi512", + "llvm.x86.avx512.pslli.w.512" => "__builtin_ia32_psllwi512", + "llvm.x86.avx512.psllv.d.512" => "__builtin_ia32_psllv16si", + "llvm.x86.avx512.psllv.q.512" => "__builtin_ia32_psllv8di", + "llvm.x86.avx512.psllv.w.128" => "__builtin_ia32_psllv8hi", + "llvm.x86.avx512.psllv.w.256" => "__builtin_ia32_psllv16hi", + "llvm.x86.avx512.psllv.w.512" => "__builtin_ia32_psllv32hi", + "llvm.x86.avx512.psra.d.512" => "__builtin_ia32_psrad512", + "llvm.x86.avx512.psra.q.128" => "__builtin_ia32_psraq128", + "llvm.x86.avx512.psra.q.256" => "__builtin_ia32_psraq256", + "llvm.x86.avx512.psra.q.512" => "__builtin_ia32_psraq512", + "llvm.x86.avx512.psra.w.512" => "__builtin_ia32_psraw512", + "llvm.x86.avx512.psrai.d.512" => "__builtin_ia32_psradi512", + "llvm.x86.avx512.psrai.q.128" => "__builtin_ia32_psraqi128", + "llvm.x86.avx512.psrai.q.256" => "__builtin_ia32_psraqi256", + "llvm.x86.avx512.psrai.q.512" => "__builtin_ia32_psraqi512", + "llvm.x86.avx512.psrai.w.512" => "__builtin_ia32_psrawi512", + "llvm.x86.avx512.psrav.d.512" => "__builtin_ia32_psrav16si", + "llvm.x86.avx512.psrav.q.128" => "__builtin_ia32_psravq128", + "llvm.x86.avx512.psrav.q.256" => "__builtin_ia32_psravq256", + "llvm.x86.avx512.psrav.q.512" => "__builtin_ia32_psrav8di", + "llvm.x86.avx512.psrav.w.128" => "__builtin_ia32_psrav8hi", + "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", + "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", + "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", + "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", + "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", + "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", + "llvm.x86.avx512.psrli.q.512" => "__builtin_ia32_psrlqi512", + "llvm.x86.avx512.psrli.w.512" => "__builtin_ia32_psrlwi512", + "llvm.x86.avx512.psrlv.d.512" => "__builtin_ia32_psrlv16si", + "llvm.x86.avx512.psrlv.q.512" => "__builtin_ia32_psrlv8di", + "llvm.x86.avx512.psrlv.w.128" => "__builtin_ia32_psrlv8hi", + "llvm.x86.avx512.psrlv.w.256" => "__builtin_ia32_psrlv16hi", + "llvm.x86.avx512.psrlv.w.512" => "__builtin_ia32_psrlv32hi", + "llvm.x86.avx512.pternlog.d.128" => "__builtin_ia32_pternlogd128", + "llvm.x86.avx512.pternlog.d.256" => "__builtin_ia32_pternlogd256", + "llvm.x86.avx512.pternlog.d.512" => "__builtin_ia32_pternlogd512", + "llvm.x86.avx512.pternlog.q.128" => "__builtin_ia32_pternlogq128", + "llvm.x86.avx512.pternlog.q.256" => "__builtin_ia32_pternlogq256", + "llvm.x86.avx512.pternlog.q.512" => "__builtin_ia32_pternlogq512", + "llvm.x86.avx512.rcp14.pd.128" => "__builtin_ia32_rcp14pd128_mask", + "llvm.x86.avx512.rcp14.pd.256" => "__builtin_ia32_rcp14pd256_mask", "llvm.x86.avx512.rcp14.pd.512" => "__builtin_ia32_rcp14pd512_mask", + "llvm.x86.avx512.rcp14.ps.128" => "__builtin_ia32_rcp14ps128_mask", + "llvm.x86.avx512.rcp14.ps.256" => "__builtin_ia32_rcp14ps256_mask", "llvm.x86.avx512.rcp14.ps.512" => "__builtin_ia32_rcp14ps512_mask", "llvm.x86.avx512.rcp14.sd" => "__builtin_ia32_rcp14sd_mask", "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", + "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", + "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", + "llvm.x86.avx512.rsqrt14.ps.128" => "__builtin_ia32_rsqrt14ps128_mask", + "llvm.x86.avx512.rsqrt14.ps.256" => "__builtin_ia32_rsqrt14ps256_mask", "llvm.x86.avx512.rsqrt14.ps.512" => "__builtin_ia32_rsqrt14ps512_mask", "llvm.x86.avx512.rsqrt14.sd" => "__builtin_ia32_rsqrt14sd_mask", "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", @@ -2581,10 +3515,211 @@ match name { "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", + "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", + "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", + "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", + "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", + "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", + "llvm.x86.avx512.vcvtsd2si64" => "__builtin_ia32_vcvtsd2si64", + "llvm.x86.avx512.vcvtsd2usi32" => "__builtin_ia32_vcvtsd2usi32", + "llvm.x86.avx512.vcvtsd2usi64" => "__builtin_ia32_vcvtsd2usi64", + "llvm.x86.avx512.vcvtss2si32" => "__builtin_ia32_vcvtss2si32", + "llvm.x86.avx512.vcvtss2si64" => "__builtin_ia32_vcvtss2si64", + "llvm.x86.avx512.vcvtss2usi32" => "__builtin_ia32_vcvtss2usi32", + "llvm.x86.avx512.vcvtss2usi64" => "__builtin_ia32_vcvtss2usi64", + "llvm.x86.avx512.vpdpbusd.128" => "__builtin_ia32_vpdpbusd128", + "llvm.x86.avx512.vpdpbusd.256" => "__builtin_ia32_vpdpbusd256", + "llvm.x86.avx512.vpdpbusd.512" => "__builtin_ia32_vpdpbusd512", + "llvm.x86.avx512.vpdpbusds.128" => "__builtin_ia32_vpdpbusds128", + "llvm.x86.avx512.vpdpbusds.256" => "__builtin_ia32_vpdpbusds256", + "llvm.x86.avx512.vpdpbusds.512" => "__builtin_ia32_vpdpbusds512", + "llvm.x86.avx512.vpdpwssd.128" => "__builtin_ia32_vpdpwssd128", + "llvm.x86.avx512.vpdpwssd.256" => "__builtin_ia32_vpdpwssd256", + "llvm.x86.avx512.vpdpwssd.512" => "__builtin_ia32_vpdpwssd512", + "llvm.x86.avx512.vpdpwssds.128" => "__builtin_ia32_vpdpwssds128", + "llvm.x86.avx512.vpdpwssds.256" => "__builtin_ia32_vpdpwssds256", + "llvm.x86.avx512.vpdpwssds.512" => "__builtin_ia32_vpdpwssds512", + "llvm.x86.avx512.vpermi2var.d.128" => "__builtin_ia32_vpermi2vard128", + "llvm.x86.avx512.vpermi2var.d.256" => "__builtin_ia32_vpermi2vard256", + "llvm.x86.avx512.vpermi2var.d.512" => "__builtin_ia32_vpermi2vard512", + "llvm.x86.avx512.vpermi2var.hi.128" => "__builtin_ia32_vpermi2varhi128", + "llvm.x86.avx512.vpermi2var.hi.256" => "__builtin_ia32_vpermi2varhi256", + "llvm.x86.avx512.vpermi2var.hi.512" => "__builtin_ia32_vpermi2varhi512", + "llvm.x86.avx512.vpermi2var.pd.128" => "__builtin_ia32_vpermi2varpd128", + "llvm.x86.avx512.vpermi2var.pd.256" => "__builtin_ia32_vpermi2varpd256", + "llvm.x86.avx512.vpermi2var.pd.512" => "__builtin_ia32_vpermi2varpd512", + "llvm.x86.avx512.vpermi2var.ps.128" => "__builtin_ia32_vpermi2varps128", + "llvm.x86.avx512.vpermi2var.ps.256" => "__builtin_ia32_vpermi2varps256", + "llvm.x86.avx512.vpermi2var.ps.512" => "__builtin_ia32_vpermi2varps512", + "llvm.x86.avx512.vpermi2var.q.128" => "__builtin_ia32_vpermi2varq128", + "llvm.x86.avx512.vpermi2var.q.256" => "__builtin_ia32_vpermi2varq256", + "llvm.x86.avx512.vpermi2var.q.512" => "__builtin_ia32_vpermi2varq512", + "llvm.x86.avx512.vpermi2var.qi.128" => "__builtin_ia32_vpermi2varqi128", + "llvm.x86.avx512.vpermi2var.qi.256" => "__builtin_ia32_vpermi2varqi256", + "llvm.x86.avx512.vpermi2var.qi.512" => "__builtin_ia32_vpermi2varqi512", + "llvm.x86.avx512.vpermilvar.pd.512" => "__builtin_ia32_vpermilvarpd512", + "llvm.x86.avx512.vpermilvar.ps.512" => "__builtin_ia32_vpermilvarps512", + "llvm.x86.avx512.vpmadd52h.uq.128" => "__builtin_ia32_vpmadd52huq128", + "llvm.x86.avx512.vpmadd52h.uq.256" => "__builtin_ia32_vpmadd52huq256", + "llvm.x86.avx512.vpmadd52h.uq.512" => "__builtin_ia32_vpmadd52huq512", + "llvm.x86.avx512.vpmadd52l.uq.128" => "__builtin_ia32_vpmadd52luq128", + "llvm.x86.avx512.vpmadd52l.uq.256" => "__builtin_ia32_vpmadd52luq256", + "llvm.x86.avx512.vpmadd52l.uq.512" => "__builtin_ia32_vpmadd52luq512", + "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_128", + "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_256", + "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_512", + "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_256", + "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_512", + "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_128", + "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_256", + "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_512", + "llvm.x86.avx512fp16.add.ph.512" => "__builtin_ia32_addph512", + "llvm.x86.avx512fp16.div.ph.512" => "__builtin_ia32_divph512", + "llvm.x86.avx512fp16.mask.add.sh.round" => "__builtin_ia32_addsh_round_mask", + "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask", + "llvm.x86.avx512fp16.mask.div.sh.round" => "__builtin_ia32_divsh_round_mask", + "llvm.x86.avx512fp16.mask.fpclass.sh" => "__builtin_ia32_fpclasssh_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.128" => "__builtin_ia32_getexpph128_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.256" => "__builtin_ia32_getexpph256_mask", + "llvm.x86.avx512fp16.mask.getexp.ph.512" => "__builtin_ia32_getexpph512_mask", + "llvm.x86.avx512fp16.mask.getexp.sh" => "__builtin_ia32_getexpsh128_round_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.128" => "__builtin_ia32_getmantph128_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.256" => "__builtin_ia32_getmantph256_mask", + "llvm.x86.avx512fp16.mask.getmant.ph.512" => "__builtin_ia32_getmantph512_mask", + "llvm.x86.avx512fp16.mask.getmant.sh" => "__builtin_ia32_getmantsh_round_mask", + "llvm.x86.avx512fp16.mask.max.sh.round" => "__builtin_ia32_maxsh_round_mask", + "llvm.x86.avx512fp16.mask.min.sh.round" => "__builtin_ia32_minsh_round_mask", + "llvm.x86.avx512fp16.mask.mul.sh.round" => "__builtin_ia32_mulsh_round_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.128" => "__builtin_ia32_rcpph128_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.256" => "__builtin_ia32_rcpph256_mask", + "llvm.x86.avx512fp16.mask.rcp.ph.512" => "__builtin_ia32_rcpph512_mask", + "llvm.x86.avx512fp16.mask.rcp.sh" => "__builtin_ia32_rcpsh_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.128" => "__builtin_ia32_reduceph128_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.256" => "__builtin_ia32_reduceph256_mask", + "llvm.x86.avx512fp16.mask.reduce.ph.512" => "__builtin_ia32_reduceph512_mask", + "llvm.x86.avx512fp16.mask.reduce.sh" => "__builtin_ia32_reducesh_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.128" => "__builtin_ia32_rndscaleph_128_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.256" => "__builtin_ia32_rndscaleph_256_mask", + "llvm.x86.avx512fp16.mask.rndscale.ph.512" => "__builtin_ia32_rndscaleph_mask", + "llvm.x86.avx512fp16.mask.rndscale.sh" => "__builtin_ia32_rndscalesh_round_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.128" => "__builtin_ia32_rsqrtph128_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.256" => "__builtin_ia32_rsqrtph256_mask", + "llvm.x86.avx512fp16.mask.rsqrt.ph.512" => "__builtin_ia32_rsqrtph512_mask", + "llvm.x86.avx512fp16.mask.rsqrt.sh" => "__builtin_ia32_rsqrtsh_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.128" => "__builtin_ia32_scalefph128_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.256" => "__builtin_ia32_scalefph256_mask", + "llvm.x86.avx512fp16.mask.scalef.ph.512" => "__builtin_ia32_scalefph512_mask", + "llvm.x86.avx512fp16.mask.scalef.sh" => "__builtin_ia32_scalefsh_round_mask", + "llvm.x86.avx512fp16.mask.sub.sh.round" => "__builtin_ia32_subsh_round_mask", + "llvm.x86.avx512fp16.mask.vcvtdq2ph.128" => "__builtin_ia32_vcvtdq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.128" => "__builtin_ia32_vcvtpd2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.256" => "__builtin_ia32_vcvtpd2ph256_mask", + "llvm.x86.avx512fp16.mask.vcvtpd2ph.512" => "__builtin_ia32_vcvtpd2ph512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.128" => "__builtin_ia32_vcvtph2dq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.256" => "__builtin_ia32_vcvtph2dq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2dq.512" => "__builtin_ia32_vcvtph2dq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.128" => "__builtin_ia32_vcvtph2pd128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.256" => "__builtin_ia32_vcvtph2pd256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2pd.512" => "__builtin_ia32_vcvtph2pd512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.128" => "__builtin_ia32_vcvtph2psx128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.256" => "__builtin_ia32_vcvtph2psx256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2psx.512" => "__builtin_ia32_vcvtph2psx512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.128" => "__builtin_ia32_vcvtph2qq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.256" => "__builtin_ia32_vcvtph2qq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2qq.512" => "__builtin_ia32_vcvtph2qq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.128" => "__builtin_ia32_vcvtph2udq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.256" => "__builtin_ia32_vcvtph2udq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2udq.512" => "__builtin_ia32_vcvtph2udq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.128" => "__builtin_ia32_vcvtph2uqq128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.256" => "__builtin_ia32_vcvtph2uqq256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uqq.512" => "__builtin_ia32_vcvtph2uqq512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.128" => "__builtin_ia32_vcvtph2uw128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.256" => "__builtin_ia32_vcvtph2uw256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2uw.512" => "__builtin_ia32_vcvtph2uw512_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.128" => "__builtin_ia32_vcvtph2w128_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.256" => "__builtin_ia32_vcvtph2w256_mask", + "llvm.x86.avx512fp16.mask.vcvtph2w.512" => "__builtin_ia32_vcvtph2w512_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.128" => "__builtin_ia32_vcvtps2phx128_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.256" => "__builtin_ia32_vcvtps2phx256_mask", + "llvm.x86.avx512fp16.mask.vcvtps2phx.512" => "__builtin_ia32_vcvtps2phx512_mask", + "llvm.x86.avx512fp16.mask.vcvtqq2ph.128" => "__builtin_ia32_vcvtqq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtqq2ph.256" => "__builtin_ia32_vcvtqq2ph256_mask", + "llvm.x86.avx512fp16.mask.vcvtsd2sh.round" => "__builtin_ia32_vcvtsd2sh_round_mask", + "llvm.x86.avx512fp16.mask.vcvtsh2sd.round" => "__builtin_ia32_vcvtsh2sd_round_mask", + "llvm.x86.avx512fp16.mask.vcvtsh2ss.round" => "__builtin_ia32_vcvtsh2ss_round_mask", + "llvm.x86.avx512fp16.mask.vcvtss2sh.round" => "__builtin_ia32_vcvtss2sh_round_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.128" => "__builtin_ia32_vcvttph2dq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.256" => "__builtin_ia32_vcvttph2dq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2dq.512" => "__builtin_ia32_vcvttph2dq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.128" => "__builtin_ia32_vcvttph2qq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.256" => "__builtin_ia32_vcvttph2qq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2qq.512" => "__builtin_ia32_vcvttph2qq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.128" => "__builtin_ia32_vcvttph2udq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.256" => "__builtin_ia32_vcvttph2udq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2udq.512" => "__builtin_ia32_vcvttph2udq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.128" => "__builtin_ia32_vcvttph2uqq128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.256" => "__builtin_ia32_vcvttph2uqq256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uqq.512" => "__builtin_ia32_vcvttph2uqq512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.128" => "__builtin_ia32_vcvttph2uw128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.256" => "__builtin_ia32_vcvttph2uw256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2uw.512" => "__builtin_ia32_vcvttph2uw512_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.128" => "__builtin_ia32_vcvttph2w128_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.256" => "__builtin_ia32_vcvttph2w256_mask", + "llvm.x86.avx512fp16.mask.vcvttph2w.512" => "__builtin_ia32_vcvttph2w512_mask", + "llvm.x86.avx512fp16.mask.vcvtudq2ph.128" => "__builtin_ia32_vcvtudq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtuqq2ph.128" => "__builtin_ia32_vcvtuqq2ph128_mask", + "llvm.x86.avx512fp16.mask.vcvtuqq2ph.256" => "__builtin_ia32_vcvtuqq2ph256_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_mask", + "llvm.x86.avx512fp16.mask.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_mask3", + "llvm.x86.avx512fp16.mask.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.128" => "__builtin_ia32_vfcmulcph128_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.256" => "__builtin_ia32_vfcmulcph256_mask", + "llvm.x86.avx512fp16.mask.vfcmul.cph.512" => "__builtin_ia32_vfcmulcph512_mask", + "llvm.x86.avx512fp16.mask.vfcmul.csh" => "__builtin_ia32_vfcmulcsh_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_mask", + "llvm.x86.avx512fp16.mask.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_mask3", + "llvm.x86.avx512fp16.mask.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.128" => "__builtin_ia32_vfmulcph128_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.256" => "__builtin_ia32_vfmulcph256_mask", + "llvm.x86.avx512fp16.mask.vfmul.cph.512" => "__builtin_ia32_vfmulcph512_mask", + "llvm.x86.avx512fp16.mask.vfmul.csh" => "__builtin_ia32_vfmulcsh_mask", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.128" => "__builtin_ia32_vfcmaddcph128_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.256" => "__builtin_ia32_vfcmaddcph256_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.cph.512" => "__builtin_ia32_vfcmaddcph512_maskz", + "llvm.x86.avx512fp16.maskz.vfcmadd.csh" => "__builtin_ia32_vfcmaddcsh_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.128" => "__builtin_ia32_vfmaddcph128_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.256" => "__builtin_ia32_vfmaddcph256_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.cph.512" => "__builtin_ia32_vfmaddcph512_maskz", + "llvm.x86.avx512fp16.maskz.vfmadd.csh" => "__builtin_ia32_vfmaddcsh_maskz", + "llvm.x86.avx512fp16.max.ph.128" => "__builtin_ia32_maxph128", + "llvm.x86.avx512fp16.max.ph.256" => "__builtin_ia32_maxph256", + "llvm.x86.avx512fp16.max.ph.512" => "__builtin_ia32_maxph512", + "llvm.x86.avx512fp16.min.ph.128" => "__builtin_ia32_minph128", + "llvm.x86.avx512fp16.min.ph.256" => "__builtin_ia32_minph256", + "llvm.x86.avx512fp16.min.ph.512" => "__builtin_ia32_minph512", + "llvm.x86.avx512fp16.mul.ph.512" => "__builtin_ia32_mulph512", + "llvm.x86.avx512fp16.sub.ph.512" => "__builtin_ia32_subph512", + "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_vcomish", + "llvm.x86.avx512fp16.vcvtsh2si32" => "__builtin_ia32_vcvtsh2si32", + "llvm.x86.avx512fp16.vcvtsh2si64" => "__builtin_ia32_vcvtsh2si64", + "llvm.x86.avx512fp16.vcvtsh2usi32" => "__builtin_ia32_vcvtsh2usi32", + "llvm.x86.avx512fp16.vcvtsh2usi64" => "__builtin_ia32_vcvtsh2usi64", + "llvm.x86.avx512fp16.vcvtsi2sh" => "__builtin_ia32_vcvtsi2sh", + "llvm.x86.avx512fp16.vcvtsi642sh" => "__builtin_ia32_vcvtsi642sh", + "llvm.x86.avx512fp16.vcvttsh2si32" => "__builtin_ia32_vcvttsh2si32", + "llvm.x86.avx512fp16.vcvttsh2si64" => "__builtin_ia32_vcvttsh2si64", + "llvm.x86.avx512fp16.vcvttsh2usi32" => "__builtin_ia32_vcvttsh2usi32", + "llvm.x86.avx512fp16.vcvttsh2usi64" => "__builtin_ia32_vcvttsh2usi64", + "llvm.x86.avx512fp16.vcvtusi2sh" => "__builtin_ia32_vcvtusi2sh", + "llvm.x86.avx512fp16.vcvtusi642sh" => "__builtin_ia32_vcvtusi642sh", + "llvm.x86.avx512fp16.vfmaddsub.ph.128" => "__builtin_ia32_vfmaddsubph", + "llvm.x86.avx512fp16.vfmaddsub.ph.256" => "__builtin_ia32_vfmaddsubph256", "llvm.x86.bmi.bextr.32" => "__builtin_ia32_bextr_u32", "llvm.x86.bmi.bextr.64" => "__builtin_ia32_bextr_u64", "llvm.x86.bmi.bzhi.32" => "__builtin_ia32_bzhi_si", @@ -2593,6 +3728,20 @@ match name { "llvm.x86.bmi.pdep.64" => "__builtin_ia32_pdep_di", "llvm.x86.bmi.pext.32" => "__builtin_ia32_pext_si", "llvm.x86.bmi.pext.64" => "__builtin_ia32_pext_di", + "llvm.x86.cldemote" => "__builtin_ia32_cldemote", + "llvm.x86.clflushopt" => "__builtin_ia32_clflushopt", + "llvm.x86.clrssbsy" => "__builtin_ia32_clrssbsy", + "llvm.x86.clui" => "__builtin_ia32_clui", + "llvm.x86.clwb" => "__builtin_ia32_clwb", + "llvm.x86.clzero" => "__builtin_ia32_clzero", + "llvm.x86.directstore32" => "__builtin_ia32_directstore_u32", + "llvm.x86.directstore64" => "__builtin_ia32_directstore_u64", + "llvm.x86.enqcmd" => "__builtin_ia32_enqcmd", + "llvm.x86.enqcmds" => "__builtin_ia32_enqcmds", + "llvm.x86.flags.read.u32" => "__builtin_ia32_readeflags_u32", + "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", + "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", + "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", @@ -2637,16 +3786,115 @@ match name { "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", + "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", + "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", + "llvm.x86.fxsave" => "__builtin_ia32_fxsave", + "llvm.x86.fxsave64" => "__builtin_ia32_fxsave64", + "llvm.x86.incsspd" => "__builtin_ia32_incsspd", + "llvm.x86.incsspq" => "__builtin_ia32_incsspq", + "llvm.x86.invpcid" => "__builtin_ia32_invpcid", + "llvm.x86.ldtilecfg" => "__builtin_ia32_tile_loadconfig", + "llvm.x86.ldtilecfg.internal" => "__builtin_ia32_tile_loadconfig_internal", + "llvm.x86.llwpcb" => "__builtin_ia32_llwpcb", + "llvm.x86.loadiwkey" => "__builtin_ia32_loadiwkey", + "llvm.x86.lwpins32" => "__builtin_ia32_lwpins32", + "llvm.x86.lwpins64" => "__builtin_ia32_lwpins64", + "llvm.x86.lwpval32" => "__builtin_ia32_lwpval32", + "llvm.x86.lwpval64" => "__builtin_ia32_lwpval64", "llvm.x86.mmx.emms" => "__builtin_ia32_emms", "llvm.x86.mmx.femms" => "__builtin_ia32_femms", + "llvm.x86.mmx.maskmovq" => "__builtin_ia32_maskmovq", + "llvm.x86.mmx.movnt.dq" => "__builtin_ia32_movntq", + "llvm.x86.mmx.packssdw" => "__builtin_ia32_packssdw", + "llvm.x86.mmx.packsswb" => "__builtin_ia32_packsswb", + "llvm.x86.mmx.packuswb" => "__builtin_ia32_packuswb", + "llvm.x86.mmx.padd.b" => "__builtin_ia32_paddb", + "llvm.x86.mmx.padd.d" => "__builtin_ia32_paddd", + "llvm.x86.mmx.padd.q" => "__builtin_ia32_paddq", + "llvm.x86.mmx.padd.w" => "__builtin_ia32_paddw", + "llvm.x86.mmx.padds.b" => "__builtin_ia32_paddsb", + "llvm.x86.mmx.padds.w" => "__builtin_ia32_paddsw", + "llvm.x86.mmx.paddus.b" => "__builtin_ia32_paddusb", + "llvm.x86.mmx.paddus.w" => "__builtin_ia32_paddusw", + "llvm.x86.mmx.palignr.b" => "__builtin_ia32_palignr", + "llvm.x86.mmx.pand" => "__builtin_ia32_pand", + "llvm.x86.mmx.pandn" => "__builtin_ia32_pandn", + "llvm.x86.mmx.pavg.b" => "__builtin_ia32_pavgb", + "llvm.x86.mmx.pavg.w" => "__builtin_ia32_pavgw", + "llvm.x86.mmx.pcmpeq.b" => "__builtin_ia32_pcmpeqb", + "llvm.x86.mmx.pcmpeq.d" => "__builtin_ia32_pcmpeqd", + "llvm.x86.mmx.pcmpeq.w" => "__builtin_ia32_pcmpeqw", + "llvm.x86.mmx.pcmpgt.b" => "__builtin_ia32_pcmpgtb", + "llvm.x86.mmx.pcmpgt.d" => "__builtin_ia32_pcmpgtd", + "llvm.x86.mmx.pcmpgt.w" => "__builtin_ia32_pcmpgtw", + "llvm.x86.mmx.pextr.w" => "__builtin_ia32_vec_ext_v4hi", + "llvm.x86.mmx.pinsr.w" => "__builtin_ia32_vec_set_v4hi", + "llvm.x86.mmx.pmadd.wd" => "__builtin_ia32_pmaddwd", + "llvm.x86.mmx.pmaxs.w" => "__builtin_ia32_pmaxsw", + "llvm.x86.mmx.pmaxu.b" => "__builtin_ia32_pmaxub", + "llvm.x86.mmx.pmins.w" => "__builtin_ia32_pminsw", + "llvm.x86.mmx.pminu.b" => "__builtin_ia32_pminub", + "llvm.x86.mmx.pmovmskb" => "__builtin_ia32_pmovmskb", + "llvm.x86.mmx.pmulh.w" => "__builtin_ia32_pmulhw", + "llvm.x86.mmx.pmulhu.w" => "__builtin_ia32_pmulhuw", + "llvm.x86.mmx.pmull.w" => "__builtin_ia32_pmullw", + "llvm.x86.mmx.pmulu.dq" => "__builtin_ia32_pmuludq", + "llvm.x86.mmx.por" => "__builtin_ia32_por", + "llvm.x86.mmx.psad.bw" => "__builtin_ia32_psadbw", + "llvm.x86.mmx.psll.d" => "__builtin_ia32_pslld", + "llvm.x86.mmx.psll.q" => "__builtin_ia32_psllq", + "llvm.x86.mmx.psll.w" => "__builtin_ia32_psllw", + "llvm.x86.mmx.pslli.d" => "__builtin_ia32_pslldi", + "llvm.x86.mmx.pslli.q" => "__builtin_ia32_psllqi", + "llvm.x86.mmx.pslli.w" => "__builtin_ia32_psllwi", + "llvm.x86.mmx.psra.d" => "__builtin_ia32_psrad", + "llvm.x86.mmx.psra.w" => "__builtin_ia32_psraw", + "llvm.x86.mmx.psrai.d" => "__builtin_ia32_psradi", + "llvm.x86.mmx.psrai.w" => "__builtin_ia32_psrawi", + "llvm.x86.mmx.psrl.d" => "__builtin_ia32_psrld", + "llvm.x86.mmx.psrl.q" => "__builtin_ia32_psrlq", + "llvm.x86.mmx.psrl.w" => "__builtin_ia32_psrlw", + "llvm.x86.mmx.psrli.d" => "__builtin_ia32_psrldi", + "llvm.x86.mmx.psrli.q" => "__builtin_ia32_psrlqi", + "llvm.x86.mmx.psrli.w" => "__builtin_ia32_psrlwi", + "llvm.x86.mmx.psub.b" => "__builtin_ia32_psubb", + "llvm.x86.mmx.psub.d" => "__builtin_ia32_psubd", + "llvm.x86.mmx.psub.q" => "__builtin_ia32_psubq", + "llvm.x86.mmx.psub.w" => "__builtin_ia32_psubw", + "llvm.x86.mmx.psubs.b" => "__builtin_ia32_psubsb", + "llvm.x86.mmx.psubs.w" => "__builtin_ia32_psubsw", + "llvm.x86.mmx.psubus.b" => "__builtin_ia32_psubusb", + "llvm.x86.mmx.psubus.w" => "__builtin_ia32_psubusw", + "llvm.x86.mmx.punpckhbw" => "__builtin_ia32_punpckhbw", + "llvm.x86.mmx.punpckhdq" => "__builtin_ia32_punpckhdq", + "llvm.x86.mmx.punpckhwd" => "__builtin_ia32_punpckhwd", + "llvm.x86.mmx.punpcklbw" => "__builtin_ia32_punpcklbw", + "llvm.x86.mmx.punpckldq" => "__builtin_ia32_punpckldq", + "llvm.x86.mmx.punpcklwd" => "__builtin_ia32_punpcklwd", + "llvm.x86.mmx.pxor" => "__builtin_ia32_pxor", + "llvm.x86.monitorx" => "__builtin_ia32_monitorx", + "llvm.x86.movdir64b" => "__builtin_ia32_movdir64b", + "llvm.x86.mwaitx" => "__builtin_ia32_mwaitx", "llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128", + "llvm.x86.pclmulqdq.256" => "__builtin_ia32_pclmulqdq256", + "llvm.x86.pclmulqdq.512" => "__builtin_ia32_pclmulqdq512", + "llvm.x86.ptwrite32" => "__builtin_ia32_ptwrite32", + "llvm.x86.ptwrite64" => "__builtin_ia32_ptwrite64", "llvm.x86.rdfsbase.32" => "__builtin_ia32_rdfsbase32", "llvm.x86.rdfsbase.64" => "__builtin_ia32_rdfsbase64", "llvm.x86.rdgsbase.32" => "__builtin_ia32_rdgsbase32", "llvm.x86.rdgsbase.64" => "__builtin_ia32_rdgsbase64", + "llvm.x86.rdpid" => "__builtin_ia32_rdpid", "llvm.x86.rdpmc" => "__builtin_ia32_rdpmc", + "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", + "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", + "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", + "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", + "llvm.x86.senduipi" => "__builtin_ia32_senduipi", + "llvm.x86.serialize" => "__builtin_ia32_serialize", + "llvm.x86.setssbsy" => "__builtin_ia32_setssbsy", "llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1", "llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2", "llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte", @@ -2654,6 +3902,7 @@ match name { "llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1", "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", + "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", @@ -2663,10 +3912,16 @@ match name { "llvm.x86.sse.comile.ss" => "__builtin_ia32_comile", "llvm.x86.sse.comilt.ss" => "__builtin_ia32_comilt", "llvm.x86.sse.comineq.ss" => "__builtin_ia32_comineq", + "llvm.x86.sse.cvtpd2pi" => "__builtin_ia32_cvtpd2pi", + "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd", + "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps", + "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi", "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", + "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi", + "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi", "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", @@ -2676,6 +3931,7 @@ match name { "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", + "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw", "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", @@ -2861,33 +4117,89 @@ match name { "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", + "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb", "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", + "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd", "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", + "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw", "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", + "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd", "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", + "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw", "llvm.x86.ssse3.phadd.sw.128" => "__builtin_ia32_phaddsw128", + "llvm.x86.ssse3.phadd.w" => "__builtin_ia32_phaddw", "llvm.x86.ssse3.phadd.w.128" => "__builtin_ia32_phaddw128", + "llvm.x86.ssse3.phsub.d" => "__builtin_ia32_phsubd", "llvm.x86.ssse3.phsub.d.128" => "__builtin_ia32_phsubd128", + "llvm.x86.ssse3.phsub.sw" => "__builtin_ia32_phsubsw", "llvm.x86.ssse3.phsub.sw.128" => "__builtin_ia32_phsubsw128", + "llvm.x86.ssse3.phsub.w" => "__builtin_ia32_phsubw", "llvm.x86.ssse3.phsub.w.128" => "__builtin_ia32_phsubw128", + "llvm.x86.ssse3.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw", "llvm.x86.ssse3.pmadd.ub.sw.128" => "__builtin_ia32_pmaddubsw128", + "llvm.x86.ssse3.pmul.hr.sw" => "__builtin_ia32_pmulhrsw", "llvm.x86.ssse3.pmul.hr.sw.128" => "__builtin_ia32_pmulhrsw128", + "llvm.x86.ssse3.pshuf.b" => "__builtin_ia32_pshufb", "llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128", + "llvm.x86.ssse3.psign.b" => "__builtin_ia32_psignb", "llvm.x86.ssse3.psign.b.128" => "__builtin_ia32_psignb128", + "llvm.x86.ssse3.psign.d" => "__builtin_ia32_psignd", "llvm.x86.ssse3.psign.d.128" => "__builtin_ia32_psignd128", + "llvm.x86.ssse3.psign.w" => "__builtin_ia32_psignw", "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", + "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", + "llvm.x86.stui" => "__builtin_ia32_stui", "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", + "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", + "llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal", + "llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd", + "llvm.x86.tdpbssd.internal" => "__builtin_ia32_tdpbssd_internal", + "llvm.x86.tdpbsud" => "__builtin_ia32_tdpbsud", + "llvm.x86.tdpbsud.internal" => "__builtin_ia32_tdpbsud_internal", + "llvm.x86.tdpbusd" => "__builtin_ia32_tdpbusd", + "llvm.x86.tdpbusd.internal" => "__builtin_ia32_tdpbusd_internal", + "llvm.x86.tdpbuud" => "__builtin_ia32_tdpbuud", + "llvm.x86.tdpbuud.internal" => "__builtin_ia32_tdpbuud_internal", + "llvm.x86.testui" => "__builtin_ia32_testui", + "llvm.x86.tileloadd64" => "__builtin_ia32_tileloadd64", + "llvm.x86.tileloadd64.internal" => "__builtin_ia32_tileloadd64_internal", + "llvm.x86.tileloaddt164" => "__builtin_ia32_tileloaddt164", + "llvm.x86.tileloaddt164.internal" => "__builtin_ia32_tileloaddt164_internal", + "llvm.x86.tilerelease" => "__builtin_ia32_tilerelease", + "llvm.x86.tilestored64" => "__builtin_ia32_tilestored64", + "llvm.x86.tilestored64.internal" => "__builtin_ia32_tilestored64_internal", + "llvm.x86.tilezero" => "__builtin_ia32_tilezero", + "llvm.x86.tilezero.internal" => "__builtin_ia32_tilezero_internal", + "llvm.x86.tpause" => "__builtin_ia32_tpause", + "llvm.x86.umonitor" => "__builtin_ia32_umonitor", + "llvm.x86.umwait" => "__builtin_ia32_umwait", "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", + "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", + "llvm.x86.vgf2p8affineinvqb.256" => "__builtin_ia32_vgf2p8affineinvqb_v32qi", + "llvm.x86.vgf2p8affineinvqb.512" => "__builtin_ia32_vgf2p8affineinvqb_v64qi", + "llvm.x86.vgf2p8affineqb.128" => "__builtin_ia32_vgf2p8affineqb_v16qi", + "llvm.x86.vgf2p8affineqb.256" => "__builtin_ia32_vgf2p8affineqb_v32qi", + "llvm.x86.vgf2p8affineqb.512" => "__builtin_ia32_vgf2p8affineqb_v64qi", + "llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi", + "llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi", + "llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi", + "llvm.x86.wbinvd" => "__builtin_ia32_wbinvd", + "llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd", "llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32", "llvm.x86.wrfsbase.64" => "__builtin_ia32_wrfsbase64", "llvm.x86.wrgsbase.32" => "__builtin_ia32_wrgsbase32", "llvm.x86.wrgsbase.64" => "__builtin_ia32_wrgsbase64", + "llvm.x86.wrpkru" => "__builtin_ia32_wrpkru", + "llvm.x86.wrssd" => "__builtin_ia32_wrssd", + "llvm.x86.wrssq" => "__builtin_ia32_wrssq", + "llvm.x86.wrussd" => "__builtin_ia32_wrussd", + "llvm.x86.wrussq" => "__builtin_ia32_wrussq", "llvm.x86.xabort" => "__builtin_ia32_xabort", "llvm.x86.xbegin" => "__builtin_ia32_xbegin", "llvm.x86.xend" => "__builtin_ia32_xend", @@ -2955,6 +4267,8 @@ match name { "llvm.x86.xop.vpshld" => "__builtin_ia32_vpshld", "llvm.x86.xop.vpshlq" => "__builtin_ia32_vpshlq", "llvm.x86.xop.vpshlw" => "__builtin_ia32_vpshlw", + "llvm.x86.xresldtrk" => "__builtin_ia32_xresldtrk", + "llvm.x86.xsusldtrk" => "__builtin_ia32_xsusldtrk", "llvm.x86.xtest" => "__builtin_ia32_xtest", // xcore "llvm.xcore.bitrev" => "__builtin_bitrev", diff --git a/tools/generate_intrinsics.py b/tools/generate_intrinsics.py new file mode 100644 index 00000000000..a1e28c3181c --- /dev/null +++ b/tools/generate_intrinsics.py @@ -0,0 +1,229 @@ +import json +import os +import re +import sys +import subprocess +from os import walk + + +def run_command(command, cwd=None): + p = subprocess.Popen(command, cwd=cwd) + if p.wait() != 0: + print("command `{}` failed...".format(" ".join(command))) + sys.exit(1) + + +def clone_repository(repo_name, path, repo_url, sub_path=None): + if os.path.exists(path): + while True: + choice = input("There is already a `{}` folder, do you want to update it? [y/N]".format(repo_name)) + if choice == "" or choice.lower() == "n": + print("Skipping repository update.") + return + elif choice.lower() == "y": + print("Updating repository...") + run_command(["git", "pull", "origin"], cwd=path) + return + else: + print("Didn't understand answer...") + print("Cloning {} repository...".format(repo_name)) + if sub_path is None: + run_command(["git", "clone", repo_url, "--depth", "1", path]) + else: + run_command(["git", "clone", repo_url, "--filter=tree:0", "--no-checkout", path]) + run_command(["git", "sparse-checkout", "init"], cwd=path) + run_command(["git", "sparse-checkout", "set", "add", sub_path], cwd=path) + run_command(["git", "checkout"], cwd=path) + + +def append_intrinsic(array, intrinsic_name, translation): + array.append((intrinsic_name, translation)) + + +def extract_instrinsics(intrinsics, file): + print("Extracting intrinsics from `{}`...".format(file)) + with open(file, "r", encoding="utf8") as f: + content = f.read() + + lines = content.splitlines() + pos = 0 + current_arch = None + while pos < len(lines): + line = lines[pos].strip() + if line.startswith("let TargetPrefix ="): + current_arch = line.split('"')[1].strip() + if len(current_arch) == 0: + current_arch = None + elif current_arch is None: + pass + elif line == "}": + current_arch = None + elif line.startswith("def "): + content = "" + while not content.endswith(";") and not content.endswith("}") and pos < len(lines): + line = lines[pos].split(" // ")[0].strip() + content += line + pos += 1 + entries = re.findall('GCCBuiltin<"(\\w+)">', content) + if len(entries) > 0: + intrinsic = content.split("def ")[1].strip().split(":")[0].strip() + intrinsic = intrinsic.split("_") + if len(intrinsic) < 2 or intrinsic[0] != "int": + continue + intrinsic[0] = "llvm" + intrinsic = ".".join(intrinsic) + if current_arch not in intrinsics: + intrinsics[current_arch] = [] + for entry in entries: + append_intrinsic(intrinsics[current_arch], intrinsic, entry) + continue + pos += 1 + continue + print("Done!") + + +def extract_instrinsics_from_llvm(llvm_path, intrinsics): + files = [] + intrinsics_path = os.path.join(llvm_path, "llvm/include/llvm/IR") + for (dirpath, dirnames, filenames) in walk(intrinsics_path): + files.extend([os.path.join(intrinsics_path, f) for f in filenames if f.endswith(".td")]) + + for file in files: + extract_instrinsics(intrinsics, file) + + +def append_translation(json_data, p, array): + it = json_data["index"][p] + content = it["docs"].split('`') + if len(content) != 5: + return + append_intrinsic(array, content[1], content[3]) + + +def extract_instrinsics_from_llvmint(llvmint, intrinsics): + archs = [ + "AMDGPU", + "aarch64", + "arm", + "cuda", + "hexagon", + "mips", + "nvvm", + "ppc", + "ptx", + "x86", + "xcore", + ] + + json_file = os.path.join(llvmint, "target/doc/llvmint.json") + if not os.path.exists(json_file): + # We need to regenerate the documentation! + run_command( + ["cargo", "rustdoc", "--", "-Zunstable-options", "--output-format", "json"], + cwd=llvmint, + ) + with open(json_file, "r", encoding="utf8") as f: + json_data = json.loads(f.read()) + for p in json_data["paths"]: + it = json_data["paths"][p] + if it["crate_id"] != 0: + # This is from an external crate. + continue + if it["kind"] != "function": + # We're only looking for functions. + continue + # if len(it["path"]) == 2: + # # This is a "general" intrinsic, not bound to a specific arch. + # append_translation(json_data, p, general) + # continue + if len(it["path"]) != 3 or it["path"][1] not in archs: + continue + arch = it["path"][1] + if arch not in intrinsics: + intrinsics[arch] = [] + append_translation(json_data, p, intrinsics[arch]) + + +def fill_intrinsics(intrinsics, from_intrinsics, all_intrinsics): + for arch in from_intrinsics: + if arch not in intrinsics: + intrinsics[arch] = [] + for entry in from_intrinsics[arch]: + if entry[0] in all_intrinsics: + if all_intrinsics[entry[0]] == entry[1]: + # This is a "full" duplicate, both the LLVM instruction and the GCC + # translation are the same. + continue + intrinsics[arch].append((entry[0], entry[1], True)) + else: + intrinsics[arch].append((entry[0], entry[1], False)) + all_intrinsics[entry[0]] = entry[1] + + +def update_intrinsics(llvm_path, llvmint): + intrinsics_llvm = {} + intrinsics_llvmint = {} + all_intrinsics = {} + + extract_instrinsics_from_llvm(llvm_path, intrinsics_llvm) + extract_instrinsics_from_llvmint(llvmint, intrinsics_llvmint) + + intrinsics = {} + # We give priority to translations from LLVM over the ones from llvmint. + fill_intrinsics(intrinsics, intrinsics_llvm, all_intrinsics) + fill_intrinsics(intrinsics, intrinsics_llvmint, all_intrinsics) + + archs = [arch for arch in intrinsics] + archs.sort() + + output_file = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "../src/intrinsic/archs.rs", + ) + print("Updating content of `{}`...".format(output_file)) + with open(output_file, "w", encoding="utf8") as out: + out.write("// File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py`\n") + out.write("// DO NOT EDIT IT!\n") + out.write("match name {\n") + for arch in archs: + if len(intrinsics[arch]) == 0: + continue + intrinsics[arch].sort(key=lambda x: (x[0], x[2])) + out.write(' // {}\n'.format(arch)) + for entry in intrinsics[arch]: + if entry[2] == True: # if it is a duplicate + out.write(' // [DUPLICATE]: "{}" => "{}",\n'.format(entry[0], entry[1])) + else: + out.write(' "{}" => "{}",\n'.format(entry[0], entry[1])) + out.write(' _ => unimplemented!("***** unsupported LLVM intrinsic {}", name),\n') + out.write("}\n") + print("Done!") + + +def main(): + llvm_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvm-project", + ) + llvmint_path = os.path.join( + os.path.dirname(os.path.abspath(__file__)), + "llvmint", + ) + + # First, we clone the LLVM repository if it's not already here. + clone_repository( + "llvm-project", + llvm_path, + "https://github.com/llvm/llvm-project", + sub_path="llvm/include/llvm/IR", + ) + clone_repository( + "llvmint", + llvmint_path, + "https://github.com/GuillaumeGomez/llvmint", + ) + update_intrinsics(llvm_path, llvmint_path) + + +if __name__ == "__main__": + sys.exit(main()) |