diff options
| -rw-r--r-- | src/base.rs | 22 | ||||
| -rw-r--r-- | src/builder.rs | 2 | ||||
| -rw-r--r-- | src/common.rs | 14 |
3 files changed, 33 insertions, 5 deletions
diff --git a/src/base.rs b/src/base.rs index 19c981309d7..2f688fd66b2 100644 --- a/src/base.rs +++ b/src/base.rs @@ -83,7 +83,7 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx2"); // FIXME(antoyo): the following causes an illegal instruction on vmovdqu64 in std_example on my CPU. // Only add if the CPU supports it. - /*context.add_command_line_option("-mavx512f"); + context.add_command_line_option("-mavx512f"); context.add_command_line_option("-msha"); context.add_command_line_option("-mpclmul"); context.add_command_line_option("-mfma"); @@ -91,7 +91,25 @@ pub fn compile_codegen_unit<'tcx>(tcx: TyCtxt<'tcx>, cgu_name: Symbol, supports_ context.add_command_line_option("-mavx512vpopcntdq"); context.add_command_line_option("-mavx512vl"); context.add_command_line_option("-m64"); - context.add_command_line_option("-mbmi");*/ + context.add_command_line_option("-mbmi"); + context.add_command_line_option("-mgfni"); + context.add_command_line_option("-mavxvnni"); + context.add_command_line_option("-mavx512vnni"); + context.add_command_line_option("-mavx512bw"); + context.add_command_line_option("-mf16c"); + context.add_command_line_option("-mavx512bitalg"); + context.add_command_line_option("-maes"); + context.add_command_line_option("-mxsavec"); + context.add_command_line_option("-mbmi2"); + context.add_command_line_option("-mavx512bf16"); + context.add_command_line_option("-mrtm"); + context.add_command_line_option("-mvaes"); + context.add_command_line_option("-mvpclmulqdq"); + context.add_command_line_option("-mavx"); + context.add_command_line_option("-mavx512vbmi2"); + context.add_command_line_option("-mavx512vbmi"); + context.add_command_line_option("-mavx512ifma"); + context.add_command_line_option("-mavx512cd"); for arg in &tcx.sess.opts.cg.llvm_args { context.add_command_line_option(arg); } diff --git a/src/builder.rs b/src/builder.rs index 4aad171cb78..08930387ccb 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -213,7 +213,7 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { let actual_ty = actual_val.get_type(); if expected_ty != actual_ty { - if !actual_ty.is_vector() && !expected_ty.is_vector() && actual_ty.is_integral() && expected_ty.is_integral() { + if !actual_ty.is_vector() && !expected_ty.is_vector() && (actual_ty.is_integral() && expected_ty.is_integral()) || (actual_ty.get_pointee().is_some() && expected_ty.get_pointee().is_some()) { self.context.new_cast(None, actual_val, expected_ty) } else if on_stack_param_indices.contains(&index) { diff --git a/src/common.rs b/src/common.rs index ce341406eaf..e0e35bea782 100644 --- a/src/common.rs +++ b/src/common.rs @@ -177,8 +177,18 @@ impl<'gcc, 'tcx> ConstMethods<'tcx> for CodegenCx<'gcc, 'tcx> { } let value = self.const_uint_big(self.type_ix(bitsize), data); - // TODO(bjorn3): assert size is correct - self.const_bitcast(value, ty) + let bytesize = layout.size(self).bytes(); + if bitsize > 1 && ty.is_integral() && bytesize as u32 == ty.get_size() { + // NOTE: since the intrinsic _xabort is called with a bitcast, which + // is non-const, but expects a constant, do a normal cast instead of a bitcast. + // FIXME(antoyo): fix bitcast to work in constant contexts. + // TODO: perhaps only use bitcast for pointers? + self.context.new_cast(None, value, ty) + } + else { + // TODO(bjorn3): assert size is correct + self.const_bitcast(value, ty) + } } Scalar::Ptr(ptr, _size) => { let (alloc_id, offset) = ptr.into_parts(); |