diff options
| -rw-r--r-- | src/tools/miri/src/shims/x86/avx.rs | 11 | ||||
| -rw-r--r-- | src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx.rs | 5 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/tools/miri/src/shims/x86/avx.rs b/src/tools/miri/src/shims/x86/avx.rs index 0d2977b7b6f..f36bb4826e4 100644 --- a/src/tools/miri/src/shims/x86/avx.rs +++ b/src/tools/miri/src/shims/x86/avx.rs @@ -338,6 +338,17 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> { this.write_scalar(Scalar::from_i32(res.into()), dest)?; } + // Used to implement the `_mm256_zeroupper` and `_mm256_zeroall` functions. + // These function clear out the upper 128 bits of all avx registers or + // zero out all avx registers respectively. + "vzeroupper" | "vzeroall" => { + // These functions are purely a performance hint for the CPU. + // Any registers currently in use will be saved beforehand by the + // compiler, making these functions no-ops. + + // The only thing that needs to be ensured is the correct calling convention. + let [] = this.check_shim(abi, Abi::C { unwind: false }, link_name, args)?; + } _ => return Ok(EmulateItemResult::NotSupported), } Ok(EmulateItemResult::NeedsReturn) diff --git a/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx.rs b/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx.rs index 7d43cc596ae..728f57d48f1 100644 --- a/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx.rs +++ b/src/tools/miri/tests/pass/shims/x86/intrinsics-x86-avx.rs @@ -1342,6 +1342,11 @@ unsafe fn test_avx() { assert_eq!(r, 1); } test_mm_testnzc_ps(); + + // These intrinsics are functionally no-ops. The only thing + // that needs to be tested is that they can be executed. + _mm256_zeroupper(); + _mm256_zeroall(); } #[target_feature(enable = "sse2")] |