diff options
Diffstat (limited to 'src/libcore')
| -rw-r--r-- | src/libcore/iter/iterator.rs | 3 | ||||
| -rw-r--r-- | src/libcore/str/lossy.rs | 7 | ||||
| -rw-r--r-- | src/libcore/sync/atomic.rs | 16 |
3 files changed, 13 insertions, 13 deletions
diff --git a/src/libcore/iter/iterator.rs b/src/libcore/iter/iterator.rs index fd4189ef50d..3063cb1a7df 100644 --- a/src/libcore/iter/iterator.rs +++ b/src/libcore/iter/iterator.rs @@ -519,7 +519,7 @@ pub trait Iterator { /// element. /// /// `map()` transforms one iterator into another, by means of its argument: - /// something that implements `FnMut`. It produces a new iterator which + /// something that implements [`FnMut`]. It produces a new iterator which /// calls this closure on each element of the original iterator. /// /// If you are good at thinking in types, you can think of `map()` like this: @@ -533,6 +533,7 @@ pub trait Iterator { /// more idiomatic to use [`for`] than `map()`. /// /// [`for`]: ../../book/ch03-05-control-flow.html#looping-through-a-collection-with-for + /// [`FnMut`]: ../../std/ops/trait.FnMut.html /// /// # Examples /// diff --git a/src/libcore/str/lossy.rs b/src/libcore/str/lossy.rs index 186d6adbc91..52abd8f9952 100644 --- a/src/libcore/str/lossy.rs +++ b/src/libcore/str/lossy.rs @@ -62,18 +62,15 @@ impl<'a> Iterator for Utf8LossyChunksIter<'a> { } const TAG_CONT_U8: u8 = 128; - fn unsafe_get(xs: &[u8], i: usize) -> u8 { - unsafe { *xs.get_unchecked(i) } - } fn safe_get(xs: &[u8], i: usize) -> u8 { - if i >= xs.len() { 0 } else { unsafe_get(xs, i) } + *xs.get(i).unwrap_or(&0) } let mut i = 0; while i < self.source.len() { let i_ = i; - let byte = unsafe_get(self.source, i); + let byte = unsafe { *self.source.get_unchecked(i) }; i += 1; if byte < 128 { diff --git a/src/libcore/sync/atomic.rs b/src/libcore/sync/atomic.rs index 56d3b429fdb..27eeb045bb1 100644 --- a/src/libcore/sync/atomic.rs +++ b/src/libcore/sync/atomic.rs @@ -173,11 +173,11 @@ unsafe impl<T> Sync for AtomicPtr<T> {} /// Atomic memory orderings /// -/// Memory orderings limit the ways that both the compiler and CPU may reorder -/// instructions around atomic operations. At its most restrictive, -/// "sequentially consistent" atomics allow neither reads nor writes -/// to be moved either before or after the atomic operation; on the other end -/// "relaxed" atomics allow all reorderings. +/// Memory orderings specify the way atomic operations synchronize memory. +/// In its weakest [`Relaxed`][Ordering::Relaxed], only the memory directly touched by the +/// operation is synchronized. On the other hand, a store-load pair of [`SeqCst`][Ordering::SeqCst] +/// operations synchronize other memory while additionally preserving a total order of such +/// operations across all threads. /// /// Rust's memory orderings are [the same as /// LLVM's](https://llvm.org/docs/LangRef.html#memory-model-for-concurrent-operations). @@ -185,6 +185,8 @@ unsafe impl<T> Sync for AtomicPtr<T> {} /// For more information see the [nomicon]. /// /// [nomicon]: ../../../nomicon/atomics.html +/// [Ordering::Relaxed]: #variant.Relaxed +/// [Ordering::SeqCst]: #variant.SeqCst #[stable(feature = "rust1", since = "1.0.0")] #[derive(Copy, Clone, Debug)] #[non_exhaustive] @@ -234,8 +236,8 @@ pub enum Ordering { /// For loads it uses [`Acquire`] ordering. For stores it uses the [`Release`] ordering. /// /// Notice that in the case of `compare_and_swap`, it is possible that the operation ends up - /// not performing any store and hence it has just `Acquire` ordering. However, - /// `AcqRel` will never perform [`Relaxed`] accesses. + /// not performing any store and hence it has just [`Acquire`] ordering. However, + /// [`AcqRel`][`AcquireRelease`] will never perform [`Relaxed`] accesses. /// /// This ordering is only applicable for operations that combine both loads and stores. /// |
