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-Zfixed-x18
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Fix AArch64InlineAsmReg::emit
Currently, this method uses `self as u32 - Self::x0 as u32` to get register index:
https://github.com/rust-lang/rust/blob/36780360b62320a61e2234b17ec600e8e4785509/compiler/rustc_target/src/asm/aarch64.rs#L204
However, this is incorrect for reasons explained in the following comment:
https://github.com/rust-lang/rust/blob/36780360b62320a61e2234b17ec600e8e4785509/compiler/rustc_codegen_llvm/src/asm.rs#L544-L549
r? ``@Amanieu``
``@rustbot`` label O-AArch64 +A-inline-assembly
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Signed-off-by: rongfu.leng <lenronfu@gmail.com>
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The previous commit updated `rustfmt.toml` appropriately. This commit is
the outcome of running `x fmt --all` with the new formatting options.
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Fixes #121593
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Convert all the crates that have had their diagnostic migration
completed (except save_analysis because that will be deleted soon and
apfloat because of the licensing problem).
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Arm's FEAT_FP and Feat_AdvSIMD describe the same thing on AArch64:
The Neon unit, which handles both floating point and SIMD instructions.
Moreover, a configuration for AArch64 must include both or neither.
Arm says "entirely proprietary" toolchains may omit floating point:
https://developer.arm.com/documentation/102374/0101/Data-processing---floating-point
In the Programmer's Guide for Armv8-A, Arm says AArch64 can have
both FP and Neon or neither in custom implementations:
https://developer.arm.com/documentation/den0024/a/AArch64-Floating-point-and-NEON
In "Bare metal boot code for Armv8-A", enabling Neon and FP
is just disabling the same trap flag:
https://developer.arm.com/documentation/dai0527/a
In an unlikely future where "Neon and FP" become unrelated,
we can add "[+-]fp" as its own feature flag.
Until then, we can simplify programming with Rust on AArch64 by
folding both into "[+-]neon", which is valid as it supersets both.
"[+-]neon" is retained for niche uses such as firmware, kernels,
"I just hate floats", and so on.
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Checking of asm! register operands now properly takes function
attributes such as #[target_feature] and #[instruction_set] into
account.
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The previous approach of checking for the reserve-r9 target feature
didn't actually work because LLVM only sets this feature very late when
initializing the per-function subtarget.
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Previously these were entirely disallowed, except for r11 which was
allowed by accident.
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This avoids unnecessary monomorphizations in codegen backends
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This saves a couple of Symbol::intern calls
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the current target.
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These are needed to properly express a function call ABI using a clobber
list, even though we don't support passing actual values into/out of
these registers.
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