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AgeCommit message (Expand)AuthorLines
2025-09-14RISC-V: Improvements of inline assembly usesTsukasa OI-3/+18
2025-09-11RISC-V: "Lower" requirements of `aes64im`Tsukasa OI-1/+1
2025-02-23mark riscv intrinsics as safeusamoi-66/+22
2025-02-09Apply missing_unsafe_on_externEric Huss-1/+1
2023-10-29Fix more missing/incorrect feature specificationsAmanieu d'Antras-0/+12
2023-10-29Add tracking issue for RISC-V intrinsicsAmanieu d'Antras-0/+3
2023-09-25Add missing `aes64im` of RISC-V Zk extensionGijs Burghoorn-0/+27
2023-09-22Fix: #1464 for rv64 zkGijs Burghoorn-20/+10
2023-08-31Fix: Remove assert_instr for RISCV, see #1464Gijs Burghoorn-10/+20
2023-08-31Fix: Add constant for assert_instrGijs Burghoorn-11/+2
2023-08-31Fix: Remove unused arch::asm importsGijs Burghoorn-2/+0
2023-08-31Impr: Remove pack instructions as instrinsicsGijs Burghoorn-34/+0
2023-08-31Fix: Utilize LLVM intrinsics where possibleGijs Burghoorn-95/+41
2023-08-31Fix: Change to 'rustc_legacy_const_generics'Gijs Burghoorn-35/+17
2023-08-31Fix: Assembly mistakes in RISC-V Zk extensionsGijs Burghoorn-2/+2
2023-08-31Implement RISC-V Zk extension intrinsicsGijs Burghoorn-0/+392
2022-02-06riscv: K extension (part 1), floating-point control and state register (#1278)Luo Jia-4/+4
2022-01-05More RISC-V instructions in `core::arch` (#1271)Luo Jia-0/+49