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2025-05-03Pr feedback for instruction & hookup CI for aarch64_beJames Barford-Evans-0/+72
2025-05-03fix - aarch64_be testsJames Barford-Evans-6/+8
2025-05-03Fix errors in incorrect SAE and ROUNDING parameterssayantn-78/+123
2025-05-01Implement `sha512`, `sm3` and `sm4` intrinsicssayantn-32/+521
2025-05-01Fix `stdarch-verify`sayantn-2/+2
2025-04-29Add `avx512vl` requirement to testsuite for avx512fp16 128 and 256 bitsayantn-26/+26
2025-04-29Fix errors in decoupling avx512vl and avx512dq from avx512fp16sayantn-92/+106
2025-04-29Fix CI errors due to alignment issues in msvcsayantn-35/+142
2025-04-23Remove workarounds for llvm/llvm-project#98306sayantn-6/+14
2025-04-23run `powerpc64le` `assert_instr` on CIFolkert de Vries-2/+2
2025-04-21use 'unadjusted' ABI for wasm LLVM intrinsicsRalf Jung-4/+4
2025-04-20Replace `cfg(stdarch_intel_sde)` with `STDARCH_TEST_SKIP_FUNCTION`sayantn-7/+0
2025-04-20Re-enable all conditionally-disabled x86 `assert_instr` testssayantn-341/+101
2025-04-17allow unnecessary transmutesbendn-1/+2
2025-04-17add `vec_extract`, `vec_insert`, `vec_promote` and `vec_insert_and_zero`Folkert de Vries-0/+243
2025-04-17Change void* type for `gather`/`scatter` intrinsicssayantn-186/+198
2025-04-17Change void* type for `cvt_storeu` intrinsicssayantn-81/+81
2025-04-17Change void* type for `compressstore` intrinsicssayantn-65/+57
2025-04-17Change void* type for 3 intrinsicssayantn-8/+8
2025-04-11fix broken intra doc linksbendn-6/+6
2025-03-27allow unnecessary transmutesbendn-0/+1
2025-03-26make documentation headers consistentFolkert de Vries-41/+86
2025-03-26add `s390x` to the module docsFolkert de Vries-0/+2
2025-03-25pr feedback - remove the commented out `vcombine_f16`James Barford-Evans-17/+2
2025-03-25refactor - arm_shared intrinsics are now YAML, where possible use anchorJames Barford-Evans-7095/+7270
2025-03-24sse42: Add unsafe blocks around unsafe function callsVadim Petrochenkov-10/+10
2025-03-24Minor correction to __m512d documentation.David Pathakjee-1/+1
2025-03-20use consistent wording around the 'undefined' intrinsics, and slightly expand...Ralf Jung-29/+45
2025-03-20Incldue loongarch64 in the list of other architecturesWANG Rui-0/+2
2025-03-16move unsafe pointer writes to the surfaceFolkert de Vries-63/+70
2025-03-16shink the size of type signaturesFolkert de Vries-176/+44
2025-03-16add `vec_meadd`, `vec_moadd`, `vec_mhadd` and `vec_mladd`Folkert de Vries-0/+237
2025-03-16add `vec_mulh`Folkert de Vries-0/+49
2025-03-16add `vec_mulo`Folkert de Vries-0/+49
2025-03-16add `vec_any_*` and `vec_all_*`Folkert de Vries-0/+219
2025-03-16add `vec_all_nan`, `vec_any_nan`, `vec_all_numeric` and `vec_any_numeric`Folkert de Vries-8/+88
2025-03-16add `vec_cmpeq_idx` and variationsFolkert de Vries-0/+206
2025-03-16add `vec_cmpeq` and `vec_cmpne`Folkert de Vries-0/+76
2025-03-16add `vec_cmpgt`, `vec_cmplt`, `vec_cmpge`, `vec_cmple`Folkert de Vries-0/+112
2025-03-16let's not use `&mut` until we get confirmation it's OKFolkert de Vries-8/+8
2025-03-16add `vec_cmprg_or_0_idx_cc` and `vec_cmpnrg_or_0_idx_cc`Folkert de Vries-0/+30
2025-03-16add `vec_cmprg_or_0_idx` and `vec_cmpnrg_or_0_idx`Folkert de Vries-24/+100
2025-03-16add `vec_cmprg_cc` and friendsFolkert de Vries-0/+40
2025-03-16add `vec_cmprg_idx` and `vec_cmpnrg_idx`Folkert de Vries-0/+36
2025-03-16add `vec_cmpnrg`Folkert de Vries-4/+34
2025-03-16add `vec_cmprg`Folkert de Vries-8/+97
2025-03-16add `vec_sld`, `vec_sldb`, `vec_sldw` and `vec_srdb`Folkert de Vries-0/+165
2025-03-16add `vec_msum_u128`Folkert de Vries-0/+45
2025-03-16add `vec_cp_until_zero` and `vec_cp_until_zero_cc`Folkert de Vries-0/+115
2025-03-16add `vec_signed` and `vec_unsigned`Folkert de Vries-0/+68