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2025-09-22Auto merge of #146683 - clarfonthey:safe-intrinsics, r=RalfJung,Amanieubors-14/+14
Mark float intrinsics with no preconditions as safe Note: for ease of reviewing, the list of safe intrinsics is sorted in the first commit, and then safe intrinsics are added in the second commit. All *recently added* float intrinsics have been correctly marked as safe to call due to the fact that they have no preconditions. This adds the remaining float intrinsics which are safe to call to the safe intrinsic list, and removes the unsafe blocks around their calls. --- Side note: this may want a try run before being added to the queue, since I'm not sure if there's any tier-2 code that uses these intrinsics that might not be tested on the usual PR flow. We've already uncovered a few places in subtrees that do this, and it's worth double-checking before clogging up the queue.
2025-09-21Mark float intrinsics with no preconditions as safeltdk-14/+14
2025-09-15Merge pull request #1921 from a4lg/riscv-inline-asm-general-improvementsSayantan Chakraborty-51/+215
RISC-V: Improvements of inline assembly uses
2025-09-15Merge pull request #1919 from sayantn/fix-vreinterpretFolkert de Vries-9286/+0
Remove big-endian swizzles from `vreinterpret`
2025-09-14RISC-V: Improvements of inline assembly usesTsukasa OI-51/+215
This commit performs various improvements (better register allocation, less register clobbering on the worst case and better readability) of RISC-V inline assembly use cases. Note that it does not change the `p` module (which defines the "P" extension draft instructions but very likely to change). 1. Use `lateout` as possible. Unlike `out(reg)` and `in(reg)` pair, `lateout(reg)` and `in(reg)` can share the same register because they state that the late-output register is written after all the reads are performed. It can improve register allocation. 2. Add `preserves_flags` option as possible. While RISC-V doesn't have _regular_ condition codes, RISC-V inline assembly in the Rust language assumes that some registers (mainly vector state registers) may be overwritten by default. By adding `preserves_flags` to the intrinsics corresponding instructions without overwriting them, it can minimize register clobbering on the worst case. 3. Use trailing semicolon. As `asm!` declares an action and it doesn't return a value by itself, it would be better to have trailing semicolon to denote that an `asm!` call is effectively a statement. 4. Make most of `asm!` calls multi-lined. `rustfmt` makes some simple (yet long) `asm!` calls multi-lined but it does not perform formatting of complex `asm!` calls with inputs and/or outputs. To keep consistency, it makes most of the `asm!` calls multi-lined.
2025-09-11Merge pull request #1918 from a4lg/riscv-aes64im-lower-requirementsSayantan Chakraborty-1/+1
RISC-V: "Lower" requirements of `aes64im`
2025-09-12Remove big-endian swizzles from `vreinterpret`sayantn-9286/+0
2025-09-11RISC-V: "Lower" requirements of `aes64im`Tsukasa OI-1/+1
This instruction is incorrectly categorized as the same one as `aes64ks1i` and `aes64ks2` (that should require `zkne || zknd` but currently require `zkne && zknd`) but `aes64im` only requires the Zknd extension. This commit fixes the category of this intrinsic (lowering the requirements from the Rust perspective but it does not actually lower it from the RISC-V perspective).
2025-09-10loongarch: Align intrinsic signatures with LLVMWANG Rui-16/+20
2025-09-06s390x: use the new `u128::funnel_shl`Folkert de Vries-15/+5
2025-09-03Merge pull request #1911 from nikic/remove-hackFolkert de Vries-12/+4
Remove some llvm workarounds
2025-09-03RISC-V: Lower requirements of `clmul` and `clmulh`Tsukasa OI-2/+2
They don't need full "Zbc" extension but only its subset: the "Zbkc" extension. Since the compiler implies `zbkc` from `zbc`, it's safe to use `#[target_feature(enable = "zbkc")]`.
2025-09-02Remove some llvm workaroundsNikita Popov-12/+4
2025-08-29use `llvm.roundeven` on armFolkert de Vries-8/+4
2025-08-21Merge pull request #1903 from folkertdev/s390x-llvm-21-fixesAmanieu d'Antras-93/+130
`s390x` llvm 21 improvements
2025-08-21use `simd_saturating_{add, sub}` on neonFolkert de Vries-288/+32
2025-08-20Merge pull request #1901 from folkertdev/wasm-read-unalignedAmanieu d'Antras-24/+14
wasm: use `{read, write}_unaligned` methods
2025-08-20Merge pull request #1899 from dpaoliello/arm64ecFolkert de Vries-2/+562
Add testing for Arm64EC Windows
2025-08-20s390x: link to a missed optimizationFolkert de Vries-0/+3
2025-08-20s390x: implement `vec_sld` using `fshl`Folkert de Vries-9/+46
2025-08-20s390x: implement `vec_subc_u128` using `overflowing_sub`Folkert de Vries-6/+4
2025-08-20s390x: implement `vec_mulo` using `core::intrinsics::simd`Folkert de Vries-36/+32
2025-08-20wasm: use `{read, write}_unaligned` methodsFolkert de Vries-24/+14
2025-08-20s390x: implement `vec_mule` using `core::intrinsics::simd`Folkert de Vries-38/+47
2025-08-20s390x: add `assert_instr` for `vec_extend`Folkert de Vries-6/+3
2025-08-20s390x: add `assert_instr` for `vec_round`Folkert de Vries-4/+2
2025-08-20s390x: define `unpack_low` using `core::intrinsics::simd`Folkert de Vries-9/+8
2025-08-20Adjust immediate for vrndscalepd testsNikita Popov-2/+2
The immediate here encodes both the rounding mode (in the low bits) and the scale (in the high bits). Make sure the scale is non-zero.
2025-08-20Work around selection failure without avx512vlNikita Popov-4/+12
2025-08-20Add missing avx512vl target featuresNikita Popov-188/+188
2025-08-20Use intrinsics for some s390x operationsNikita Popov-3/+10
2025-08-20Drop no longer needed feature gatesNikita Popov-2/+0
2025-08-14Stabilize `sse4a` and `tbm` target featuressayantn-2/+0
- remove some stabilized target features from `gate.rs`
2025-08-10Add testing for Arm64EC WindowsDaniel Paoliello-2/+562
2025-07-31Merge ref '32e7a4b92b10' from rust-lang/rustThe rustc-josh-sync Cronjob Bot-0/+10
Pull recent changes from https://github.com/rust-lang/rust via Josh. Upstream ref: 32e7a4b92b109c24e9822c862a7c74436b50e564 Filtered ref: 56d8aa13f54944edb711f3bdd7013b082dbaa65b This merge was created using https://github.com/rust-lang/josh-sync.
2025-07-25Allow ffi_unwind_calls for `arch::wasm32::throw`Alisa Sireneva-0/+10
2025-07-25Merge pull request #1879 from heiher/loong-simd-unified-typesFolkert de Vries-4431/+4647
loongarch: Use unified data types for SIMD intrinsics
2025-07-25loongarch: Use unified data types for SIMD intrinsicsWANG Rui-4431/+4647
2025-07-24Add non-temporal note for maskmoveu_si128Aurelia Molzer-1/+10
Like any other non-temporal instructions this has additional safety requirements due to the mismatch with the Rust memory model. It is vital to know when using this instruction.
2025-07-22work around not being able to project out of SIMD values any moreFolkert de Vries-4/+10
2025-07-18Merge pull request #1860 from folkertdev/stdarch-test-cleanupAmanieu d'Antras-95/+335
`stdarch-test`: various cleanups
2025-07-18loongarch: Mark SIMD intrinsics without memory access as safeWANG Rui-2872/+2872
2025-07-18loongarch: Mark partial basic intrinsics as safeWANG Rui-44/+41
2025-07-17test for the high version of a number of instructionsFolkert de Vries-29/+29
2025-07-15`aarch64`: check for `trn1` and `trn2`Folkert de Vries-17/+85
2025-07-15`aarch64`: check for `uzp1` and `uzp2`Folkert de Vries-17/+85
2025-07-15`aarch64`: check for `zip1` and `zip2`Folkert de Vries-28/+132
2025-07-15s390x: fix tests that matched on prefix of instructionFolkert de Vries-4/+4
2025-07-15Merge pull request #1872 from folkertdev/aarch64-horizontal-addAmanieu d'Antras-195/+55
`aarch64`: use `intrinsics::simd` for horizontal add and `abs`
2025-07-15`aarch64`: implement `vabs` using `instrinsics::simd`Folkert de Vries-21/+15
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