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This reverts commit 85572dc298f5222902c9b200cebf5d045e769a83.
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Because the current lowest requirements to run the Linux kernel on RISC-V is
RV{32,64}IMA (with 32 general purpose registers) plus some features,
RV32E (with only 16 GPRs) is not currently supported.
Since it's not sure whether current implemented method will work for future
Linux versions even if the minimum requirements are lowered, the support for
RV32E (to be more specific, an attempt to do that) is removed for now.
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Until in-kernel feature detection is implemented, runtime detection of
privileged extensions is temporally removed along with features themselves
since none of such privileged features are stable.
Co-Authored-By: Taiki Endo <te316e89@gmail.com>
Co-Authored-By: Amanieu d'Antras <amanieu@gmail.com>
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This commit implements `riscv_hwprobe`-based feature detection as available
on newer versions of the Linux kernel. It also queries whether the vector
extensions are enabled using `prctl` but this is not supported on QEMU's
userland emulator (as of version 9.2.3) and use the auxiliary vector
as a fallback.
Currently, all extensions discoverable from the Linux kernel version 6.14
and related extension groups (except "Supm", which reports the existence of
`prctl`-based pointer masking control and too OS-dependent) are implemented.
Co-Authored-By: Taiki Endo <te316e89@gmail.com>
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This commit adds the OS-independent extension implication logic for RISC-V.
It implements:
1. Regular implication (A → B)
a. "the extension A implies the extension B"
b. "the extension A requires the extension B"
c. "the extension A depends on the extension B"
2. Extension group or shorthand (A == B1 & B2...)
a. "the extension A is shorthand for other extensions: B1, B2..."
b. "the extension A comprises instructions provided by B1, B2..."
This is implemented as (A → B1 & B2... + B1 & B2... → A)
where the former is a regular implication as required by specifications
and the latter is a "reverse" implication to improve usability.
and prepares for:
3. Implication with multiple requirements (A1 & A2... → B)
a. "A1 + A2 implies B"
b. (implicitly used to implement reverse implication of case 2)
Although it uses macros and iterators, good optimizers turn the series of
implications into fast bit-manipulation operations.
In the case 2 (extension group or shorthand; where a superset extension
is just a collection of other subextensions and provides no features by
a superset itself), specifications do specify that an extension group
implies its members but not vice versa. However, implying an extension
group from its members would improve usability on the feature detection
(especially when the feature provider does not provide existence of such
extension group but provides existence of its members).
Similar "reverse implication" on RISC-V is implemented on LLVM.
Case 3 is implicitly used to implement reverse implication of case 2 but
there's another use case: implication with multiple requirements like
"Zcf" and "Zcd" extensions (not yet implemented in this crate for now).
To handle extension groups perfectly, we need to loop implication several
times (until they converge; normally 2 times and up to 4 times when we add
most of `riscv_hwprobe`-based features).
To make implementation of that loop possible, `cache::Initializer` is
modified to implement `PartialEq` and `Eq`.
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This is ported from Taiki Endo's branch and sorted by the `@FEATURE` order
as in `src/detect/arch/riscv.rs`.
Co-Authored-By: Taiki Endo <te316e89@gmail.com>
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The "B" extension is once abandoned (instead, it is ratified as a collection
of "Zb*" extensions). However, it is later redefined and ratified as a
superset of "Zba", "Zbb" and "Zbs" extensions (but not "Zbc" carry-less
multiplication for limited benefits and implementation cost).
Although non-functional (because feature detection is not yet implemented),
it provides the foundation to implement this extension (along with
straightforward documentation showing subsets of "B").
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The "A" extension comprises instructions provided by the "Zaamo" and
"Zalrsc" extensions. To prepare for the "Zacas" extension (which provides
compare-and-swap instructions and discoverable from Linux) which depends on
the "Zaamo" extension, it would be better to support those subsets.
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As Taiki Endo pointed out, there's a problem if we continue using
`target_pointer_width` values to detect an architecture because:
* There are separate `target_arch`s already and
* There is an experimental ABI (not ratified though): RV64ILP32.
cf. <https://lpc.events/event/17/contributions/1475/attachments/1186/2442/rv64ilp32_%20Run%20ILP32%20on%20RV64%20ISA.pdf>
Co-Authored-By: Taiki Endo <te316e89@gmail.com>
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This commit prepares common infrastructure for extension implication by
removing `enable_features` closure which makes each feature test longer
(because it needs extra `value` argument each time we test a feature).
It comes with the overhead to enable each feature separately but later
mitigated by the OS-independent extension implication logic.
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Because this function will be no longer auxvec-only, this commit adds a
comment to mark auxvec-based part.
It *does not* add a comment to "base ISA" part because it may also use
`riscv_hwprobe`-based results.
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This commit makes handling of the base ISA a separate block.
Co-Authored-By: Taiki Endo <te316e89@gmail.com>
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1. Use canonical kernel.org repository instead of the GitHub mirror.
2. Refer to the fixed commit to guarantee access.
3. Use `uapi` part to ensure that the feature detection is primarily
intended for user-mode programs.
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The author intended to split:
1. Former "I" extensions
2. Other "I"-related extensions
but incorrectly separated between "Zihpm" (a supplement of "Zicntr" which is
a former "I" extension) and "Zifencei" (a former "I" extension) while the
author intended making a separation between "Zifencei" and "Zihintpause"
(not a part of "I").
This commit fixes the separation.
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Not only moving the link to the end of the section, this commit changes
the link so that we can reach to the *ratified* ISA manuals (note that,
while the original URL (GitHub) is a good place to browse the latest
draft, it's not easy to know which is the ratified version; even
"Releases" page is not helpful since it's regularly updated).
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Some extensions are ratified at least on the ISA specification version
20240411. This commit moves such extensions.
This commit also changes that:
1. Lower indentation of "Zk*" and "Zbk*" extensions to avoid extension
groups from being misleading inside this section.
2. Raise indentation of "Zfhmin" and "Zhinxmin" extensions to show that
they are a strict subset of "Zfh" and "Zhinx" (respectively).
3. Clarify that "s" is not an extension but a feature notifying
the existence of the supervisor-level ISA.
4. Clarify that "h" is not just an existence of the hypervisor-level ISA
but is also an extension name ("H").
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RISC-V extension names are capitalized for consistency.
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update
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rust-lang/rust#138823 added five new extensions as compiler target features.
This commit reflects that fact and now checks static target features on
`std::arch::is_riscv_feature_detected!` as well.
* "Zicsr"
* "Zicntr"
* "Zihpm"
* "Zifencei"
* "Zihintpause"
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this now always uses the name as specified by the official docs
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tags
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Although the "B" extension is redefined and ratified, keeping this in the
documentation as-is have two issues:
* "B" extension is not added to `riscv.rs` yet (to be added later).
* "B" extension is ratified as a combination of "Zba", "Zbb" and "Zbs"
extensions and "Zbc" is *not* a part of "B" itself (despite that
it is listed under "B"), which makes the documentation misleading.
This commit tentatively removes the reference to the "B" extension and
replaced with "Bit Manipulation Extensions" without an extension name.
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As the version 20240411 of the RISC-V ISA Manual changed wording to
describe many of the standard extensions, this commit largely follows this
scheme in general. In many cases, words "Standard Extension" are replaced
with "Extension" following the latest ratified ISA Manual.
Some RISC-V extensions had tentative summary but it also fixes that
(e.g. "Zihintpause").
Following extensions are described in parity with corresponding extensions
using floating-point registers:
* "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
* "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
* "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
* "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers
Following extensions are named against the ISA Manual naming but
considered inconsistency inside the ISA manual:
* "Zfhmin" Extension for Minimal Half-Precision Floating-Point
ISA Manual: "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point
* "V" Extension for Vector Operations
ISA Manual: "V" Standard Extension for Vector Operations
Following extension is removed from the latest ratified ISA Manual but
named like others:
* "Zam" Extension for Misaligned Atomics
"Zb*" extensions are described like "Extension for ..." using partial
summary per extension (including cryptography-related "Zbk*" extensions).
"Zk*" extensions are described like "Cryptography Extension for ..." using
partial summary per extension (e.g. 'Zkne - NIST Suite: AES Encryption' in
the ISA Manual to '"Zkne" Cryptography Extension for NIST Suite: AES
Encryption') except following extensions:
* "Zkr" Entropy Source Extension
Following the general rule will make the description redundant.
* "Zk" Cryptography Extension for Standard scalar cryptography
The last word "extension" is removed as seemed redundant.
Link:
<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications>
(ISA Specifications, Version 20240411; published in May 2024)
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All RISC-V Features are reordered for better maintainability.
The author has a plan to add many RISC-V ratified extensions (mainly
discoverable from Linux) and this is a part of preparation.
Sections are divided as follows:
* Base ISAs
* "I"-related
* Extensions formerly a part of the base "I" extension
but divided later (now all of them are ratified).
* Other user-mode extensions "Zi*".
* "M"-related (currently "M" only)
* "A"-related
"A", "Za*" and "Ztso" which is named differently but absolutely
related to memory operations.
* Base FP extensions
* Base FP extensions using integer registers
* "C"-related (currently "C" only)
* "B"-related (except cryptography-related "Zbk*")
* Scalar cryptography extensions (including "Zbk*")
* Base Vector extensions (currently "V" only)
* Ratified privileged extensions
* Non-extensions and non-ratified extensions which is *not*
going to be ratified, at least in the draft form
The last section needs some explanation.
"S" is not an extension (although some buggy implementations such as QEMU
up to 7.0 emitted this character as well as "U" as an extension) and the
DeviceTree parser in the Linux kernel explicitly workarounds this issue.
There's no plan for ratification of the single-letter "J" extension
(there's a room for redefinition like the "B" extension but unlikely).
Instead, pointer masking extensions including "Supm" is one of the results
of the task group discussing J extension*s*.
There's also an instruction in the "Zfa" extension which accelerates
FP-to-int conversion matching JavaScript semantics.
"P" is being actively discussed (and will result in a single-letter "P"
extension and various "Zp*" extensions) but it seems there needs some time
until ratification.
And there's one Rust-specific issue: Rust implements Packed-SIMD intrinsics
based on an early draft of the "P" extension and they are *very unlikely*
kept as-is. For instance, `add16` does not follow standard RISC-V
instruction naming (ADD16 is the name from the Andes' proposal) and
going to be renamed.
Before moving "P" to above, we have to clearly understand what the final
"P" extension will be and resolve existing intrinsics.
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This commit adds indentation as suggested by the Clippy warning.
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This error occurs when the RISC-V "A" Extension is being tested.
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to fix the `unsafe_op_in_unsafe_fn` lint
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A 512-bit register is f64x8, not f64x4. Likely a copy-paste error from the _m256d documentation,
which seems correct.
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expand their docs
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RISC-V runtime feature detection macro is stabilized on Rust 1.78.0,
not Rust 1.76.0.
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