rust - https://github.com/rust-lang/rust

Age	Commit message (Collapse)	Author	Lines
2025-09-15	rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list	Tsukasa OI	-1/+1
	Despite that the `fflags` register (representing floating point exception flags) is stated as a flag register in the reference, it's not in the default clobber list of the RISC-V inline assembly and it would be better to fix it.
2025-07-22	Rename `tests/codegen` into `tests/codegen-llvm`	Guillaume Gomez	-0/+40