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authorbors <bors@rust-lang.org>2023-08-26 06:02:13 +0000
committerbors <bors@rust-lang.org>2023-08-26 06:02:13 +0000
commit766c0c0b83d4e391c6882f5af2c690888edcf42a (patch)
treebf34cc4162c388a51506242d28c579bbb02e2c1e /compiler/rustc_codegen_llvm/src
parent9334ec93541fd6963a3bfa2d2d09e3e33ac93131 (diff)
parent84e305dd93cc83cdd9378d0f6f657d8caaabfad8 (diff)
downloadrust-766c0c0b83d4e391c6882f5af2c690888edcf42a.tar.gz
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Auto merge of #115236 - scottmcm:less-vector, r=compiler-errors
Stop emitting non-power-of-two vectors in (non-portable-SIMD) codegen

Fixes #115212

It's unclear what makes this not work sometimes, since it often *does* work, so for now just disable the unusual cases.  A future PR can consider doing something smarter, but this is an easy and safe tweak that we can do to resolve the regressions for now.
Diffstat (limited to 'compiler/rustc_codegen_llvm/src')
-rw-r--r--compiler/rustc_codegen_llvm/src/type_of.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/rustc_codegen_llvm/src/type_of.rs b/compiler/rustc_codegen_llvm/src/type_of.rs
index 2be7bce115d..831645579b9 100644
--- a/compiler/rustc_codegen_llvm/src/type_of.rs
+++ b/compiler/rustc_codegen_llvm/src/type_of.rs
@@ -405,7 +405,11 @@ impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
 
         // Vectors, even for non-power-of-two sizes, have the same layout as
         // arrays but don't count as aggregate types
+        // While LLVM theoretically supports non-power-of-two sizes, and they
+        // often work fine, sometimes x86-isel deals with them horribly
+        // (see #115212) so for now only use power-of-two ones.
         if let FieldsShape::Array { count, .. } = self.layout.fields()
+            && count.is_power_of_two()
             && let element = self.field(cx, 0)
             && element.ty.is_integral()
         {